IDT82V3280DQ IDT, Integrated Device Technology Inc, IDT82V3280DQ Datasheet - Page 20

• Manufacturer Part Number: IDT82V3280DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3280DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP EP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

3.3
3.3.1
lowing technologies:
supported:
from T3. The input clock is a 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4
kHz composite clock. The 400HZ_SEL bit should be set to match the
input frequency. Any input violation that does not meet the standard
composite clock structure will induce an AMI violation. The AMI violation
is indicated by the AMI1_VIOL
AMI2_VIOL
interrupt.
clock sources can be from T1, T2 or T3.
Functional Description
IDT82V3280
Altogether 14 clocks and 1 frame sync signal are input to the device.
The device provides 14 input clock ports.
According to the input port technology, the input ports support the fol-
According to the input clock source, the following clock sources are
IN1 and IN2 support the AMI input signal only and the clock source is
IN3, IN4 and IN7 ~ IN14 support CMOS input signal only and the
• AMI
• PECL/LVDS
• CMOS
• T1: Recovered clock from STM-N or OC-n
• T2: PDH network synchronization timing
• T3: External synchronization reference timing
INPUT CLOCKS & FRAME SYNC SIGNAL
INPUT CLOCKS
2
bit is ‘1’, the occurrence of an AMI violation will trigger an
1
/ AMI2_VIOL
1
bit. If the AMI1_VIOL
2
/
20
detect whether the signal is PECL or LVDS. The clock sources can be
from T1, T2 or T3.
SONET / SDH frequency selection is controlled by the IN_SONET_SDH
bit. During reset, the default value of the IN_SONET_SDH bit is deter-
mined by the SONET/SDH pin: high for SONET and low for SDH. After
reset, the input signal on the SONET/SDH pin takes no effect.
3.3.2
pin. It is a CMOS input. The input frequency should match the setting in
the SYNC_FREQ[1:0] bits.
chronization. Refer to
details.
Table 3: Related Bit / Register in Chapter 3.3
SYNC_FREQ[1:0]
IN_SONET_SDH
IN5 and IN6 support PECL/LVDS input signal only and automatically
For SDH and SONET networks, the default frequency is different.
A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1
The frame sync input signal is used for frame sync output signal syn-
AMI1_VIOL
AMI2_VIOL
AMI1_VIOL
AMI2_VIOL
400HZ_SEL
Bit
FRAME SYNC INPUT SIGNALS
1
1
2
2
Chapter 3.13.2 Frame SYNC Output Signals
INTERRUPTS3_ENABLE_CNFG
INPUT_MODE_CNFG
INTERRUPT3_STS
IN1_CNFG
IN2_CNFG
Register
March 02, 2009
Address (Hex)
WAN PLL
14
15
0F
12
09
for