IDT82V3280DQ IDT, Integrated Device Technology Inc, IDT82V3280DQ Datasheet - Page 25

• Manufacturer Part Number: IDT82V3280DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3280DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP EP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Table 7: Input Clock Selection for T4 Path
3.6
mine the input clock selection, as shown in
Table 6: Input Clock Selection for T0 Path
pendently from T0 path, as determined by the T4_LOCK_T0 bit. When
the T4 DPLL locks to the T0 DPLL output, the T4 selected input clock is
a 77.76 MHz or 8 kHz signal from the T0 DPLL 77.76 MHz path (refer to
Chapter 3.11.5.1 T0
the T4 path locks independently from the T0 path, the T4 DPLL input
clock selection is determined by the T4_INPUT_SEL[3:0] bits. Refer to
Table
Functional Description
Table 8: External Fast Selection
IDT82V3280
Control Bits - T4_INPUT_SEL[3:0]
An input clock is selected for T0 DPLL and for T4 DPLL respectively.
For T0 path, the EXT_SW bit and the T0_INPUT_SEL[3:0] bits deter-
For T4 path, the T4 DPLL may lock to a T0 DPLL output or lock inde-
External Fast selection is done between IN3/IN5 and IN4/IN6 pairs.
Forced selection is done by setting the related registers.
FF_SRCSW (after reset)
EXT_SW
7:
1
0
other than 0000
T0 / T4 DPLL INPUT CLOCK SELECTION
Control Bits
high
low
0000
T0_INPUT_SEL[3:0]
other than 0000
Path), as determined by the T0_FOR_T4 bit. When
don’t-care
0000
IN3_SEL_PRIORITY[3:0]
other than 0000
Control Pin & Bits
Table
don’t-care
Input Clock Selection
Input Clock Selection
External Fast selection
Automatic selection
0000
Automatic selection
Forced selection
Forced selection
6:
IN4_SEL_PRIORITY[3:0]
25
ity monitoring and the related registers configuration.
3.6.1
Fast selection, only IN3/IN5 and IN4/IN6 pairs are available for selec-
tion. Refer to
(refer to
clock selection.
after reset (this pin determines the default value of the EXT_SW bit dur-
ing
IN3_SEL_PRIORITY[3:0] bits and the IN4_SEL_PRIORITY[3:0] bits, as
shown in
other than 0000
Automatic selection is done based on the results of input clocks qual-
The selected input clock is attempted to be locked in T0/T4 DPLL.
The External Fast selection is supported by T0 path only. In External
The T0 input clock selection is determined by the FF_SRCSW pin
don’t-care
0000
reset,
Chapter 3.5 Input Clock Quality
Figure 5
IN3
IN5
IN4
IN6
EXTERNAL FAST SELECTION (T0 ONLY)
Figure 5. External Fast Selection
Figure
IN4_SEL_PRIORITY[3:0] bits
IN3_SEL_PRIORITY[3:0] bits
refer
and
5. The results of input clocks quality monitoring
Table
to
8:
Chapter 2
FF_SRCSW pin
the Selected Input Clock
Monitoring) do not affect input
Pin
locked in T0 DPLL
IN5
IN3
IN4
IN6
attempted to be
Description),
March 02, 2009
WAN PLL
the