IDT82V3280DQ IDT, Integrated Device Technology Inc, IDT82V3280DQ Datasheet - Page 67

• Manufacturer Part Number: IDT82V3280DQ
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V3280DQ

• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP EP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

NOMINAL_FREQ[23:16]_CNFG - Crystal Oscillator Frequency Offset Calibration Configuration 3
T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration
Programming Information
IDT82V3280
Address: 06H
Type: Read / Write
Default Value: 00000000
Address: 07H
Type: Read / Write
Default Value: XXX0XXXX
7 - 0
Bit
NOMINAL_FRE
Q_VALUE23
7 - 5
3 - 0
Bit
4
NOMINAL_FREQ_VALUE[23:16]
7
7
-
T4_T0_SEL
Name
Name
NOMINAL_FRE
Q_VALUE22
-
-
6
-
6
Reserved.
A part of the registers are shared by T0 and T4 paths. These registers are addressed 26H ~ 2CH, 4EH, 4FH, 5AH, 5BH, 62H ~
64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path.
0: T0 path (default).
1: T4 path.
Reserved.
The NOMINAL_FREQ_VALUE[23:0] bits represent a 2’s complement signed integer. If the value is multiplied by
0.0000884, the calibration value for the master clock in ppm will be gotten.
For example, the frequency offset on OSCI is +3 ppm. Though -3 ppm should be compensated, the calibration value is
calculated as +3 ppm:
3 ÷ 0.0000884 = 33937 (Dec.) = 8490 (Hex);
So ‘008490’ should be written into these bits.
The calibration range is within ±741 ppm.
NOMINAL_FRE
Q_VALUE21
5
-
5
NOMINAL_FRE
T4_T0_SEL
Q_VALUE20
4
4
67
NOMINAL_FRE
Q_VALUE19
3
-
3
Description
Description
NOMINAL_FRE
Q_VALUE18
2
-
2
NOMINAL_FRE
Q_VALUE17
1
-
1
NOMINAL_FRE
March 02, 2009
Q_VALUE16
0
-
WAN PLL
0