LFEC10E-3F484C LATTICE SEMICONDUCTOR, LFEC10E-3F484C Datasheet - Page 22

• Manufacturer Part Number: LFEC10E-3F484C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3F484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 288
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
Signed and Unsigned with Different Widths
The DSP block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. For
unsigned operands, unused upper data bits should be filled to create a valid x9, x18 or x36 operand. For signed
two’s complement operands, sign extension of the most significant bit should be performed until x9, x18 or x36
width is reached. Table 2-8 provides an example of this.
Table 2-8. An Example of Sign Extension
OVERFLOW Flag from MAC
The sysDSP block provides an overflow output to indicate that the accumulator has overflowed. When two
unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and
overflow signal is indicated. When two positive numbers are added with a negative sum and when two negative
numbers are added with a positive sum, then the accumulator “roll-over” is said to have occurred and an overflow
signal is indicated. Note when overflow occurs the overflow flag is present for only one cycle. By counting these
overflow pulses in FPGA logic, larger accumulators can be constructed. The conditions overflow signals for signed
and unsigned operands are listed in Figure 2-23.
Figure 2-23. Accumulator Overflow/Underflow Conditions
Number Unsigned
+5
-6
0101
0110
Overflow signal is generated
for one cycle when this
boundary is crossed
000000101
000000110
Unsigned
9-bit
000000000000000101
000000000000000110
0101111100
0101111110
0101111111
0101111100
0101111101
0101111110
0101111111
1010000010
0101111101
1010000000
1010000001
1010000010
1010000000
1010000001
Unsigned
18-bit
Unsigned Operation
Signed Operation
256
257
258
255
256
255
254
252
253
254
255
252
253
254
2-19
Signed
0101
1010
111111101
111111110
111111101
000000011
000000001
111111111
111111110
000000011
000000010
000000001
000000000
111111111
000000010
000000000
Two’s Complement
Signed 9-Bits
LatticeECP/EC Family Data Sheet
000000101
111111010
+3
+2
+1
-1
-2
-3
511
510
509
0
3
2
1
0
Carry signal is generated for
boundary is crossed
one cycle when this
000000000000000101
111111111111111010
Two’s Complement
Signed 18-bits
Architecture