LFEC10E-3F484C LATTICE SEMICONDUCTOR, LFEC10E-3F484C Datasheet - Page 78

• Manufacturer Part Number: LFEC10E-3F484C
• Description: FPGA LatticeEC Family 10200 Cells 340MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFEC10E-3F484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 10200
• Maximum Internal Frequency: 340 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 288
• Ram Bits: 282624
• In System Programmability: Yes

Lattice Semiconductor
LFEC1, LFEC3, LFECP/EC6 Logic Signal Connections: 144 TQFP (Cont.)
Number
Pin
72*
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Pin Function Bank LVDS
PROGRAMN
VCCAUX
VCCIO4
VCCIO4
VCCIO3
VCCIO3
PB10A
PB10B
PB11A
PB11B
PB12A
PB12B
PB13A
PB13B
PB14A
PB14B
PB15A
PB15B
PB16B
PB17B
PR14A
PR12B
PR12A
PR11B
PR11A
PR10B
PR10A
DONE
GND5
GND4
GND3
GND4
GND3
CFG2
CFG1
CFG0
CCLK
PB8B
PB9A
PB9B
PR9B
PR9A
PR8B
PR8A
PR7B
PR7A
INITN
GND
GND
VCC
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
LFEC1
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
PCLKC5_0
DI/CSSPIN
PCLKT5_0
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
D7/SPID0
VREF1_5
VREF1_4
VREF2_4
VREF1_3
RDQS11
WRITEN
BDQS14
CS1N
CSN
Pin Function Bank LVDS
PROGRAMN
VCCAUX
VCCIO4
VCCIO4
VCCIO3
VCCIO3
PB16B
PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
PB23A
PB23B
PB24B
PB25B
PR18A
PR16B
PR16A
PR15B
PR15A
PR14B
PR14A
PR13B
PR13A
PR12B
PR12A
PR11B
PR11A
GND5
GND4
GND3
GND4
GND3
DONE
CFG2
CFG1
CFG0
CCLK
INITN
GND
GND
VCC
4-12
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
LFEC3
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
PCLKC5_0
DI/CSSPIN
PCLKT5_0
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
D7/SPID0
VREF1_5
VREF1_4
VREF2_4
VREF1_3
RDQS15
WRITEN
BDQS22
CS1N
CSN
LatticeECP/EC Family Data Sheet
Pin Function Bank LVDS
PROGRAMN
VCCAUX
VCCIO4
VCCIO4
VCCIO3
VCCIO3
PB16B
PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
PB23A
PB23B
PB24B
PB25B
PR27A
PR25B
PR25A
PR24B
PR24A
PR23B
PR23A
PR22B
PR22A
PR21B
PR21A
PR20B
PR20A
GND5
GND4
GND3
GND4
GND3
DONE
CFG2
CFG1
CFG0
CCLK
INITN
GND
GND
VCC
Pinout Information
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
LFECP6/EC6
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
C
T
C
T
C
T
C
T
C
T
C
T
RLM0_PLLC_FB_A
RLM0_PLLT_FB_A
RLM0_PLLC_IN_A
RLM0_PLLT_IN_A
Dual Function
DOUT/CSON
BUSY/SISPI
PCLKC5_0
DI/CSSPIN
PCLKT5_0
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
D7/SPID0
VREF1_5
VREF1_4
VREF2_4
VREF1_3
BDQS22
RDQS24
WRITEN
CS1N
CSN