MB86297EB01 Fujitsu, MB86297EB01 Datasheet - Page 13

• Manufacturer Part Number: MB86297EB01
• Description: BOARD, EVAL, PCI, CARMINE, MB86297
• Manufacturer: Fujitsu

Specifications of MB86297EB01

• Silicon Manufacturer: Fujitsu
• Silicon Core Number: MB86297
• Kit Contents: Board
• Features: 128Mbyte DDR SDRAM Memory, Video Outputs, Video Input
• Application Sub Type: PCI Graphics Display Controller
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MB86297EB01 Evaluation Board Manual
8 CPLD Functions
The Carmine Evaluation board incorporates a Xilinx CPLD CoolRunner ll (XC2C128-7TQ144,
U400) which is normally pre-programmed. If necessary, the device can be re-programmed using
the JTAG interface (X400) on the reverse side of the board. Use the Xilinx programming tools
(ISE) for reprogramming (www.xilinx.com).
The CPLD provides the following functions:
The on-board DIP switches (SW100) and the I2C interface of the Carmine graphics processor are
used to select the video input source for the ITU RBT-656 (RGB666) video capture interfaces of
the Carmine device. After a reset, the input source will be selected according to switch 7 and
switch 6 of SW100.
If bit 2 of the CONFIG register in the CPLD is set to logical ‘1’, the input source will be selected
from bit 1 and bit 0 of the CONFIG register. The CONFIG register is programmed via the I2C
interface of the Carmine graphic processor.
Switch 7 is equivalent to bit 1 of the CONFIG register and switch 6 is equivalent to bit 0. The
following table shows the selectable combinations:
Bit 3 of the CONFIG register sets the output enable signal of the switch FSAV430 (U201). If bit 3 is
set to logical ‘0’ (default after reset) the selected connection with switch 8 of SW100 is connected
else the connection is open.
Bit 5 and bit 4 of the CONFIG register set the switch FSAV433 (U502) and NC7SB3257 (U602). Bit
5 is equivalent to VO_CTRL1. Bit 4 is equivalent to VO_CTRL0. The CONFIG register of the CPLD
can be programmed via the I2C interface of the Carmine graphic processor.
(DIP7)
Bit 1
0
0
1
1
(DIP6)
Bit 0
0
1
0
1
Input Source
RGB input
YUV input 1
YUV input 2
No input
© 2005 Fujitsu Microelectronics Europe
Revision 1.2
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