MB86297EB01 Fujitsu, MB86297EB01 Datasheet - Page 30

• Manufacturer Part Number: MB86297EB01
• Description: BOARD, EVAL, PCI, CARMINE, MB86297
• Manufacturer: Fujitsu

Specifications of MB86297EB01

• Silicon Manufacturer: Fujitsu
• Silicon Core Number: MB86297
• Kit Contents: Board
• Features: 128Mbyte DDR SDRAM Memory, Video Outputs, Video Input
• Application Sub Type: PCI Graphics Display Controller
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

D
C
B
A
SD_CTRL[12..0]
SD_AD[15..0]
SD_D[63..0]
SD_DQM[7..0]
SD_DQS[7..0]
S D_AD[15..0]
SD_D[63..0]
SD_CTRL[12..0]
SD _DQS[7..0]
SD_DQM[7..0]
5
5
SD_DQM0
SD_DQM1
SD_DQM2
SD_DQM3
SD_DQM4
SD_DQM5
SD_DQM6
SD_DQM7
SD_DQS0
SD_DQS1
SD_DQS2
SD_DQS3
SD_DQS4
SD_DQS5
SD_DQS6
SD_DQS7
SD_CTRL0
SD_CTRL1
SD_CTRL2
SD_CTRL3
SD_CTRL4
SD_CTRL5
SD_CTRL6
SD_CTRL7
SD_CTRL8
SD_CTRL9
SD_CTRL10
SD_CTRL11
SD_CTRL12
SD_AD0
SD_AD1
SD_AD2
SD_AD3
SD_AD4
SD_AD5
SD_AD6
SD_AD7
SD_AD8
SD_AD9
SD_AD10
SD_AD11
SD_AD12
SD_AD13
SD_AD14
SD_AD15
SD_D0
SD_D1
SD_D2
SD_D3
SD_D4
SD_D5
SD_D6
SD_D7
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_D16
SD_D17
SD_D18
SD_D19
SD_D20
SD_D21
SD_D22
SD_D23
SD_D24
SD_D25
SD_D26
SD_D27
SD_D28
SD_D29
SD_D30
SD_D31
SD_D32
SD_D33
SD_D34
SD_D35
SD_D36
SD_D37
SD_D38
SD_D39
SD_D40
SD_D41
SD_D42
SD_D43
SD_D44
SD_D45
SD_D46
SD_D47
SD_D48
SD_D49
SD_D50
SD_D51
SD_D52
SD_D53
SD_D54
SD_D55
SD_D56
SD_D57
SD_D58
SD_D59
SD_D60
SD_D61
SD_D62
SD_D63
Consider DDR SDRAM
layout rules from Carmine
design guide for LOOP signals!
D CK0
DCK0#
D CK1
DCK1#
DCS#0
D CKE
DW E#
DRAS#
DCAS#
DLOOPO_0
DLOOPI_0
DLOOPO_1
DLOOPI_1
SD_D16
SD_D17
SD_D18
SD_D19
SD_D20
SD_D21
SD_D22
SD_D23
SD_DQS2
SD_AD13
SD_DQM2
DW E#
DCAS#
DRAS#
DCS#0
SD_AD14
SD_AD15
SD_AD10
SD_AD0
SD_AD1
SD_AD2
SD_AD3
SD_D48
SD_D49
SD_D50
SD_D51
SD_D52
SD_D53
SD_D54
SD_D55
SD_DQS6
SD_AD13
SD_DQM6
DW E#
DCAS#
DRAS#
DCS#0
SD_AD14
SD_AD15
SD_AD10
SD_AD0
SD_AD1
SD_AD2
SD_AD3
4
4
Consider DDR SDRAM layout
rules from Carmine design guide!
VCC25
VCC25
Place C's close to SDRAM power pins,
one of each value to each SDRAM!
Place C's close to SDRAM power pins,
one of each value to each SDRAM!
C972
10u
C986
10u
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
C973
1u
C987
1u
VDD1
DQ0
VDDQ1
DQ1
DQ2
VSSQ1
DQ3
DQ4
VDDQ2
DQ5
DQ6
VSSQ2
DQ7
NC1
VDDQ3
LDQS
NC2/A13
VDD2
NC3
LDM
WE#
CAS#
RAS#
CS#
NC4
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD3
VDD1
DQ0
VDDQ1
DQ1
DQ2
VSSQ1
DQ3
DQ4
VDDQ2
DQ5
DQ6
VSSQ2
DQ7
NC1
VDDQ3
LDQS
NC2/A13
VDD2
NC3
LDM
WE#
CAS#
RAS#
CS#
NC4
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD3
U901
DDR-RAM 16Mx16
U903
DDR-RAM 16Mx16
C974
1u
C988
1u
C975
100n
C989
100n
VDDQ5
VDDQ4
VDDQ5
VDDQ4
VSSQ5
VSSQ4
VSSQ3
VSSQ5
VSSQ4
VSSQ3
UDQS
UDQS
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
C976
100n
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
C990
100n
VSS3
VSS2
VSS1
VSS3
VSS2
VSS1
DQ9
DQ8
UDM
CKE
DQ9
DQ8
UDM
CKE
NC7
NC6
Vref
CK#
NC5
A12
A11
NC7
NC6
Vref
CK#
NC5
A12
A11
CK
A9
A8
A7
A6
A5
A4
CK
A9
A8
A7
A6
A5
A4
C977
1n
C991
1n
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VCC25
VCC25
VCC25
VCC25
SD_D31
SD_D30
SD_D29
SD_D28
SD_D27
SD_D26
SD_D25
SD_D24
SD_DQS3
SD_VREF_LW
SD_DQM3
DCK0#
D CK0
D CKE
SD_AD12
SD_AD11
SD_AD9
SD_AD8
SD_AD7
SD_AD6
SD_AD5
SD_AD4
SD_D63
SD_D62
SD_D61
SD_D60
SD_D59
SD_D58
SD_D57
SD_D56
SD_DQS7
SD_VREF_UW
SD_DQM7
DCK1#
D CK1
D CKE
SD_AD12
SD_AD11
SD_AD9
SD_AD8
SD_AD7
SD_AD6
SD_AD5
SD_AD4
Place Rxxx according to
Carmine DDR SDRAM
layout guideline!
Place Rxxx according to
Carmine DDR SDRAM
layout guideline!
Place Vref filter network directly to
the corresponding U900, U901 pins!
Place Vref filter network directly to
the corresponding U902, U903 pins!
R900
1k5
R901
1k5
R902
1k5
R903
1k5
3
3
R904
100R
R906
100R
C998
1n
C1001
1n
C1003
1n
C1006
1n
C999
100n
C1002
100n
C1004
100n
C1007
100n
SD_VREF_LW
SD_VREF_UW
L900
BLM18PG600SN1
L901
BLM18PG600SN1
VCC25
VCC25
C1000
100n
C1005
100n
SD_D0
SD_D1
SD_D2
SD_D3
SD_D4
SD_D5
SD_D6
SD_D7
SD_DQS0
SD_AD13
SD_DQM0
DW E#
DCAS#
DRAS#
DCS#0
SD_AD14
SD_AD15
SD_AD10
SD_AD0
SD_AD1
SD_AD2
SD_AD3
SD_D32
SD_D33
SD_D34
SD_D35
SD_D36
SD_D37
SD_D38
SD_D39
SD_DQS4
SD_AD13
SD_DQM4
DW E#
DCAS#
DRAS#
DCS#0
SD_AD14
SD_AD15
SD_AD10
SD_AD0
SD_AD1
SD_AD2
SD_AD3
VCC25
VCC25
Place C's close to SDRAM power pins,
one of each value to each SDRAM!
Place C's close to SDRAM power pins,
one of each value to each SDRAM!
C978
10u
C992
10u
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
C979
1u
C993
1u
U900
VDD1
DQ0
VDDQ1
DQ1
DQ2
VSSQ1
DQ3
DQ4
VDDQ2
DQ5
DQ6
VSSQ2
DQ7
NC1
VDDQ3
LDQS
NC2/A13
VDD2
NC3
LDM
WE#
CAS#
RAS#
CS#
NC4
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD3
U902
VDD1
DQ0
VDDQ1
DQ1
DQ2
VSSQ1
DQ3
DQ4
VDDQ2
DQ5
DQ6
VSSQ2
DQ7
NC1
VDDQ3
LDQS
NC2/A13
VDD2
NC3
LDM
WE#
CAS#
RAS#
CS#
NC4
BA0
BA1
AP/A10
A0
A1
A2
A3
VDD3
DDR-RAM 16Mx16
DDR-RAM 16Mx16
C980
1u
C994
1u
C981
100n
C995
100n
2
2
VSSQ5
VDDQ5
VSSQ4
VDDQ4
VSSQ3
VSSQ5
VDDQ5
VSSQ4
VDDQ4
VSSQ3
UDQS
C982
100n
UDQS
C996
100n
VSS3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VSS2
VSS1
VSS3
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
VSS2
VSS1
UDM
UDM
DQ9
DQ8
NC7
NC6
CK#
CKE
NC5
DQ9
DQ8
NC7
NC6
CK#
CKE
NC5
Vref
A12
A11
Vref
A12
A11
CK
CK
A9
A8
A7
A6
A5
A4
A9
A8
A7
A6
A5
A4
C983
1n
C997
1n
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VCC25
VCC25
VCC25
VCC25
SD_D15
SD_D14
SD_D13
SD_D12
SD_D11
SD_D10
SD_D9
SD_D8
SD_DQS1
SD_VREF_LW
SD_DQM1
DCK0#
D CK0
D CKE
SD_AD12
SD_AD11
SD_AD9
SD_AD8
SD_AD7
SD_AD6
SD_AD5
SD_AD4
SD_D47
SD_D46
SD_D45
SD_D44
SD_D43
SD_D42
SD_D41
SD_D40
SD_DQS5
SD_VREF_UW
SD_DQM5
DCK1#
D CK1
D CKE
SD_AD12
SD_AD11
SD_AD9
SD_AD8
SD_AD7
SD_AD6
SD_AD5
SD_AD4
VT_DRAM
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
Place Rxxx according to
Carmine DDR SDRAM
layout guideline!
Place Rxxx according to
Carmine DDR SDRAM
layout guideline!
RN916
50Rx4
RN917
50Rx4
RN918
50Rx4
RN919
50Rx4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
R905
100R
R907
100R
SD_DQS2
SD_DQS1
SD_DQM2
SD_DQM1
SD_DQS6
SD_DQS5
SD_DQM6
SD_DQM5
SD_DQM0
SD_DQM3
SD_DQS0
SD_DQS3
SD_DQM4
SD_DQM7
SD_DQS7
SD_DQS4
Title
Size
Date:
© mycable GmbH
Boeker Stieg 43
D-24613 Aukrug
Germany
www.mycable.de
A2
Fujitsu Carmine Evaluation Board: Carmine Subsystem: DDR SDRAM
Document Number
30100-015
Monday, November 21, 2005
VT_DRAM
1
1
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
RN900
50Rx4
RN901
50Rx4
RN902
50Rx4
RN903
50Rx4
RN904
50Rx4
RN905
50Rx4
RN906
50Rx4
RN907
50Rx4
RN908
50Rx4
RN909
50Rx4
RN910
50Rx4
RN911
50Rx4
RN912
50Rx4
RN913
50Rx4
RN914
50Rx4
RN915
50Rx4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
Sheet
SD_D0
SD_D1
SD_D2
SD_D3
SD_D4
SD_D5
SD_D6
SD_D7
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_D16
SD_D17
SD_D18
SD_D19
SD_D20
SD_D21
SD_D22
SD_D23
SD_D24
SD_D25
SD_D26
SD_D27
SD_D28
SD_D29
SD_D30
SD_D31
SD_D32
SD_D33
SD_D34
SD_D35
SD_D36
SD_D37
SD_D38
SD_D39
SD_D40
SD_D41
SD_D42
SD_D43
SD_D44
SD_D45
SD_D46
SD_D47
SD_D48
SD_D49
SD_D50
SD_D51
SD_D52
SD_D53
SD_D54
SD_D55
SD_D56
SD_D57
SD_D58
SD_D59
SD_D60
SD_D61
SD_D62
SD_D63
15
o f
15
R ev
PA11
D
C
B
A