MB86297EB01 Fujitsu, MB86297EB01 Datasheet - Page 27

• Manufacturer Part Number: MB86297EB01
• Description: BOARD, EVAL, PCI, CARMINE, MB86297
• Manufacturer: Fujitsu

Specifications of MB86297EB01

• Silicon Manufacturer: Fujitsu
• Silicon Core Number: MB86297
• Kit Contents: Board
• Features: 128Mbyte DDR SDRAM Memory, Video Outputs, Video Input
• Application Sub Type: PCI Graphics Display Controller
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

D
C
B
A
CM_VI0_SYNC[3..0]
CM_VI0_RGB[17..0]
CM_VI1_656_D[7..0]
CM_VI1_CLK
RESET#[2..0]
CONFIG[4..0]
VO0_CLK[4..0]
VO1_CLK[4..0]
JTAG[4..0]
I2C[1..0]
CM_VI1_CLK
CM_VI0_SYN C[3..0]
CM _VI0_RGB[17..0]
CM_VI1_656_D[7..0]
RESET#[2..0]
JT AG[4..0]
VO 0_CLK[4..0]
VO 1_CLK[4..0]
CONFIG[4..0]
I2C[1..0]
5
5
RESET#0
RESET#1
RESET#2
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
I2C0
I2C1
JTAG0
JTAG1
JTAG2
JTAG3
JTAG4
CM_VO0_DCLKO
VO0_CLK4
VO0_CLK1
VO0_CLK3
VO0_CLK0
CM_VO1_DCLKO
VO1_CLK0
VO1_CLK1
VO1_CLK2
VO1_CLK3
JTAG_TRST#
CARMINE_MODE0
CARMINE_MODE1
CLKSEL0
CLKSEL1
I2C _SCL
I2C _SDA
JTAG_TRST#
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK
Place R829 - R833 close to the
corresponding U801 pins!
Place R834 - R837 close to the
corresponding U802 pins!
NP
R829
R831
R833
R830
R835
R836
R838
R837
VT_DRAM
33R
33R
33R
33R
33R
33R
33R
33R
NP NP
Place R815 directly
to U800 pin D7!
TEST
1
2
3
4
1
2
3
4
Place R820 directly
to Y800 pin 3!
U801
IDT2305-1DCGI
U802
IDT2305-1DCGI
REF
CLK2
CLK1
GND
REF
CLK2
CLK1
GND
NP
Clock Buffer
Clock Buffer
IDT2305
Zero Delay
IDT2305
Zero Delay
CLKOUT
CLKOUT
CLK4
CLK3
CLK4
CLK3
CLOCK
VDD
VDD
VCC25
VCC25
8
7
6
5
8
7
6
5
R800
1k5
R809
1k5
R811
1k5
R813
1k5
4
4
C801
100n
C807
100n
C813
100n
C819
100n
R820
33R
I2C
R802
50R
S D_VREF0
S D_VREF2
C827
100n
C829
100n
VCC33
VCC33
NP
VT_DRAM
C828
10u
C830
10u
CARMINE_MODE0
CARMINE_MODE1
CLKSEL0
CLKSEL1
JTAG_TRST#
JTAG_TDI
JTAG_TMS
JTAG_TCK
I2C _SDA
I2C _SCL
CKE_START
CA RMINE_CLK_EN
R803
50R
4
3
Y800
SG8002 CA PC 14.320
VCC25
VCC25
VCC
OUT
C831
10p
C832
10p
Carmine Graphics Processor
OSC
R832
R834
R801
1k5
R810
1k5
R812
1k5
R814
1k5
Clock skew adjustment
NP
Clock skew adjustment
NP
1
2
3
4
1
2
3
4
1
2
3
4
Memory-Interface
RN825
4k7x4
RN826
4k7x4
RN827
4k7x4
33R
33R
GND
OE
C804
100n
C810
100n
C816
100n
C822
100n
8
7
6
5
8
7
6
5
8
7
6
5
VCC33
1
2
S D_VREF1
S D_VREF3
VO0_CLK2
VO1_CLK4
CA RMINE_CLK_EN
Video-Capture Interface
C824
100n
Place all DDR damping resistors
according to Carmine design guide!
Consider DDR SDRAM layout
rules from Carmine design guide!
C825
1u
L800
BLM18PG600SN1
VCC33
3
3
C826
100n
Video-Out 1
R827
33R
CM_VO1_DCLKO
PCI-Interface
Video-Out 0
Place R827, R828 directly to the
corresponding Carmine pins!
2
2
CM_V O0_HSYNC
CM _VO0_VSYNC
CM_V O1_HSYNC
CM _VO1_VSYNC
Place R823 - R826 close to the
corresponding Carmine pins!
R823
R824
R825
R826
0R
0R
0R
0R
VO0_EXT_HSYNC
VO0_EXT_VSYNC
VO1_EXT_HSYNC
VO1_EXT_VSYNC
R828
33R
CM_VO0_DCLKO
U800A
MB86297
PCI Signal Assignment
PCI_CTRL0
PCI_CTRL1
PCI_CTRL2
PCI_CTRL3
PCI_CTRL4
PCI_CTRL5
PCI_CTRL6
PCI_CTRL7
PCI_CTRL8
PCI_CTRL9
PCI_CTRL10
PCI_CTRL11
PCI_CTRL12
PCI_CTRL13
PCI_CTRL14
CLK
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
PERR#
SERR#
IDSEL
C/BE0#
C/BE1#
C/BE2#
C/BE3#
INT#
Title
Size
D ate:
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A1
SD_ CTRL[12..0]
SD_DQ S[7..0]
SD_ DQM[7..0]
SD_AD [15..0]
SD_D[63..0]
PCI33_CTRL[14..0]
PCI33 _AD[31..0]
VO1_SYNC[4..0]
VO0_SYNC[4..0]
V O0_RGB[23..0]
V O1_RGB[23..0]
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
1
1
Fujitsu Carmine Evaluation Board: Carmine Subsystem: Carmine
Document Number
30100-012
Monday, November 21, 2005
SD_CTRL[12..0]
SD_DQS[7..0]
SD_DQM[7..0]
SD_AD[15..0]
SD_D[63..0]
PCI33_CTRL[14..0]
PCI33_AD[31..0]
VO1_SYNC[4..0]
VO0_SYNC[4..0]
VO0_RGB[23..0]
VO1_RGB[23..0]
VO0_SYNC_EXT[2..0]
VO1_SYNC_EXT[2..0]
Sheet
12
o f
15
R e v
PA11
D
C
B
A