STM32L-DISCOVERY STMicroelectronics, STM32L-DISCOVERY Datasheet - Page 121

• Manufacturer Part Number: STM32L-DISCOVERY
• Description: BOARD, EVAL, STM32L-DISCOVERY
• Manufacturer: STMicroelectronics
• Series: STM32r
• Type: MCUr

Specifications of STM32L-DISCOVERY

• Kit Contents: Board, Debugger, Programmer And Compiler
• Features: 128KB Flash Plus Multiple Timers, Analogue Peripherals
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: STM32
• Silicon Family Name: STM32F1xx
• Rohs Compliant: Yes
• Contents: Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: STM32L
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STM32F205xx, STM32F207xx
Figure 56. Asynchronous multiplexed PSRAM/NOR read waveforms
Table 69.
1. C
2. Preliminary values.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
w(NE)
v(NOE_NE)
w(NOE)
h(NE_NOE)
v(A_NE)
v(NADV_NE)
w(NADV)
h(AD_NADV)
h(A_NOE)
h(BL_NOE)
v(BL_NE)
su(Data_NE)
su(Data_NOE)
h(Data_NE)
h(Data_NOE)
Symbol
L
= 15 pF.
FSMC_NBL[1:0]
FSMC_ AD[15:0]
FSMC_A[25:16]
FSMC_NADV
Asynchronous multiplexed PSRAM/NOR read timings
FSMC_NWE
FSMC_NOE
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
Address hold time after FSMC_NOE high
FSMC_BL hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
Data to FSMC_NEx high setup time
Data to FSMC_NOE high setup time
Data hold time after FSMC_NEx high
Data hold time after FSMC_NOE high
FSMC_NE
Parameter
Doc ID 15818 Rev 6
t
t
t
v(NADV_NE)
v(A_NE)
v(A_NE)
t
t
t
v(NOE_NE)
v(BL_NE)
w(NADV)
Address
Address
t
h(AD_NADV)
t
w(NE)
NBL
t
su(Data_NOE)
t
t
7T
3T
4T
–1
3
T
T
T
0
2T
2T
0
0
w(NOE)
su(Data_NE)
Data
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
t
h(NE_NOE)
Min
t
h(BL_NOE)
t
h(A_NOE)
–1.5
Electrical characteristics
– 2
– 0.5 3T
– 1
+ 24
+ 25
(1)(2)
7T
4T
0
5
T
0
HCLK
HCLK
HCLK
HCLK
Max
t
h(Data_NOE)
t
+ 1.5
h(Data_NE)
+ 2
+ 1.5
+ 2
ai14892b
121/163
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit