LE58QL02FJC Zarlink, LE58QL02FJC Datasheet - Page 14

• Manufacturer Part Number: LE58QL02FJC
• Description: SLIC 4-CH 3.3V 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE58QL02FJC

• Package: 44PLCC
• Number Of Channels Per Chip: 4
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

Notes:
1.
2.
3.
4.
5.
Transmission Characteristics
When relative levels (dBm0) are used in any of the following transmission specifications, the specification holds for any setting
of the GX gain from 0 dB to 12 dB, the GR loss from 0 dB to 12 dB, and the input attenuator (GIN) on or off.
Notes:
1.
2.
3.
4.
The CD1, CD2, C3–C5 outputs are resistive for less than a 0.8 V drop. Total current must not exceed absolute maximum ratings.
When the digitizer saturates, a resistor of 50 kΩ ±20 kΩ is connected either to AGND or to VCCA as appropriate to discharge the coupling
capacitor.
When the QLSLAC device is in the Inactive state, the analog output will present either a VREF DC output level through a 15 kΩ resistor
(VMODE = 0) or a high impedance (VMODE = 1).
If there is an external DC path from VOUT to VIN with a gain of G
by 1 / [1 – (h
Power dissipation in the Inactive state is measured with all digital inputs at VIH = VCCD and VIL = DGND and with no load connected to
VOUT1, VOUT2, VOUT3, or VOUT4.
See Figure 5 and Figure 6.
0 dBm0 input signal, 300 Hz to 3400 Hz; measurement at any other frequency, 300 Hz to 3400 Hz.
No single frequency component in the range above 3800 Hz may exceed a level of –55 dBm0.
The weighted average of the crosstalk is defined by the following equation, where C(f) is the crosstalk in dB as a function of frequency, f
= 3300 Hz, f
Table 2. 0 dBm0 Voltage Definitions with Unity Gain in X, R, GX, GR, AX, and AR
A-law digital mW or equivalent (0 dBm0)
µ-law digital mW or equivalent (0 dBm0)
±22,827 peak linear coded sine wave
Gain accuracy, D/A or A/D
Gain accuracy digital-to-digital
Gain accuracy analog-to-analog
Attenuation distortion
Single frequency distortion
Second harmonic distortion, D-A
Idle channel noise
Crosstalk
same channel
Crosstalk between channels
End-to-end group delay
Analog out
Digital out
TX or RX to TX
TX or RX to RX
1
AISN
Signal at Digital Interface
= 300 Hz, and the frequency points (f
Description
• G
DC
)].
TX to RX
RX to TX
0 dBm0, 1014 Hz
GR = 0 dB
Digital looped back
Digital input = 0
Digital input = 0
Analog V
Analog V
0 dBm0
0 dBm0
0 dBm0
SLIC imped. < 300 Ω
B = Z = 0; X = R = 1
AX = AR = 0 dB
AX = +6.02 dB and/or
AR = –6.02 dB
0 to 85° C
–40° C
0 to 85° C
–40° C
j
IN
IN
, j = 2..N) are closely spaced:
Zarlink Semiconductor Inc.
= 0 VAC
= 0 VAC
Test Conditions
(DGIN = 0)
Transmit
0.7804
0.7746
0.7804
300 Hz to 3 kHz
300 to 3400 Hz
300 to 3400 Hz
DC
14
and the AISN has a gain of h
weighted
unweighted
A-law
µ-law
A-law
µ-law
1014 Hz, Average
1014 Hz, Average
(DGIN = 1)
Transmit
0.5024
0.4987
0.5024
–0.125
–0.25
–0.30
–0.30
–0.40
–0.25
–0.25
Min
AISN
, then the output offset will be multiplied
Typ
0
0
Receive
0.5024
0.4987
0.5024
+0.125
+0.25
+0.30
+0.30
+0.40
+0.25
+0.25
Max
–46
–55
–68
–55
–78
–68
–75
–75
–76
–78
678
12
16
dBm0p
dBm0p
dBrnc0
dBm0p
dBrnc0
dBm0
dBm0
dBm0
Unit
dB
µs
Vrms
Unit
Note
3, 6
3, 6
1
2
3
3
3
3
4
5
N