LE58QL02FJC Zarlink, LE58QL02FJC Datasheet - Page 45

• Manufacturer Part Number: LE58QL02FJC
• Description: SLIC 4-CH 3.3V 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE58QL02FJC

• Package: 44PLCC
• Number Of Channels Per Chip: 4
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

50/51h Write/Read AISN and Analog Gains
Disable Input Attenuator (GIN)
Transmit Analog Gain
Receive Analog Loss
AISN coefficient
* Power Up and Hardware Reset (RST) Value = 00h.
52/53h Write/Read SLIC Device Input/Output Register
RSVD
Pins CD1, CD2, and C3 through C5 are set to 1 or 0. The data appears latched on the CD1, CD2, and C3 through C5 SLIC
* Power Up and Hardware Reset (RST) Value = 00h
54/55h Write/Read SLIC Input/Output Direction, Read Status Bits
RSVD
Command
I/O Data
Command
I/O Data
Command
Input Data
R/W = 0: Write
R/W = 1: Read
R/W = 0: Write
R/W = 1: Read
R/W = 0: Write
R/W = 1: Read
h
AISN
DGIN = 0*
DGIN = 1
AX = 0*
AX = 1
AR = 0*
AR = 1
AISN = 0* – 31
The Impedance Scaling Network (AISN) gain can be varied from −0.9375 • GIN to +0.9375 • GIN in
multiples of 0.0625 • GIN.
The gain coefficient is decoded using the following equation:
where h
a value of AISN = 0000* indicates a gain of 0 (cutoff).
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
device I/O pins, provided they were set in the Output mode (see Command 54/55h on page
data sent to any of the pins set to the Input mode is latched, but does not appear at the pins. The CD1B bit
is only valid if the E1 Multiplex mode is enabled (EE1 = 1).
Reserved for future use. Always write as 0, but 0 is not guaranteed when read.
=
0.0625 GIN
AISN
is the gain of the AISN. A value of AISN = 10000 turns on the Full Digital Loopback mode and
•
Input attenuator on
Input attenuator off
0 dB gain
6.02 dB gain
0 dB loss
6.02 dB loss
See below (Default value = 0)
[
(
16 AISN4
RSVD
RSVD
DGIN
D
0
D
D
•
7
0
0
7
7
Zarlink Semiconductor Inc.
CSTAT
RSVD
+
D
AX
D
D
1
1
1
6
8 AISN3
6
6
•
45
CFAIL
CD1B
AR
D
D
D
0
0
0
5
5
5
+
4 AISN2
•
AISN4
IOD5
C5
D
D
D
1
1
1
4
4
4
+
AISN3
IOD4
2 AISN1
C4
D
D
D
0
0
0
3
3
3
•
AISN2
IOD3
D
D
C3
D
0
0
1
2
2
2
+
AISN0
AISN1
IOD2
CD2
D
D
D
0
1
0
1
1
1
) 16
–
AISN0
]
IOD1
CD1
R/W
R/W
R/W
D
D
D
0
0
0
page
45). The