IP4035CX24/LF/P,13 NXP Semiconductors, IP4035CX24/LF/P,13 Datasheet - Page 5
![IC EMI FILTER ESD PROTECT 24CSP](/photos/16/19/161957/lpip4041cx25_sml.jpg)
IP4035CX24/LF/P,13
Manufacturer Part Number
IP4035CX24/LF/P,13
Description
IC EMI FILTER ESD PROTECT 24CSP
Manufacturer
NXP Semiconductors
Datasheet
1.IP4035CX24LFP13.pdf
(12 pages)
Specifications of IP4035CX24/LF/P,13
Capacitance
50pF
Package / Case
24-CSP
Resistance In Ohms
1.00K
Operating Voltage
- 0.5 V to 5.5 V
Channels
10 Channels
Breakdown Voltage
6 V to 15 V
Termination Style
SMD/SMT
Power Dissipation Pd
420 mW
Operating Temperature Range
- 45 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Tolerance
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
934061587135
NXP Semiconductors
7. Application information
IP4035CX24_1
Product data sheet
7.1 Insertion loss
The insertion loss measurement configuration of a typical 50 Ω NetWork Analyzer (NWA)
system for evaluation of the IP4035CX24 is shown in
The insertion loss of all channels for frequencies up to 6 GHz is displayed in
The insertion loss is measured with a test PCB utilizing laser drilled micro-via holes that
connect the PCB ground plane to the IP4035CX24 ground pins.
Fig 3.
Fig 4.
(10) Channel 7 (pins C2 and E2).
(1) Channel 1 (pins B1 and D1).
(2) Channel 10 (pins C5 and E5).
(3) Channel 6 (pins C1 and E1).
(4) Channel 5 (pins B5 and D5).
(5) Channel 9 (pins C4 and E4).
(6) Channel 8 (pins C3 and E3).
(7) Channel 3 (pins B2 and D3).
(8) Channel 2 (pins A2 and D2).
(9) Channel 4 (pins A5 and D4).
(dB)
s
21
Frequency response measurement configuration
10
20
30
40
50
60
70
Measured insertion loss magnitudes
0
1
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 12 February 2010
10-channel integrated filter network with ESD input protection
10
50
V gen
IN
TEST BOARD
DUT
10
2
(10)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
OUT
Figure
001aai755
50
10
3.
3
IP4035CX24
f (MHz)
001aak011
© NXP B.V. 2010. All rights reserved.
10
Figure
4
4.
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