ISL3873BIK Intersil, ISL3873BIK Datasheet - Page 22

• Manufacturer Part Number: ISL3873BIK
• Manufacturer: Intersil

Specifications of ISL3873BIK

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The terms: 1, 2, 3, and 4 are defined below for
5.5Mbps and 11Mbps.
This formula creates 8 complex chips (LSB to MSB) that are
transmitted LSB first. The coding is a form of the generalized
Hadamard transform encoding where the phase 1 is added
to all code chips, 2 is added to all odd code chips, 3 is
added to all odd pairs of code chips and 4 is added to all
odd quads of code chips.
The phase 1 modifies the phase of all code chips of the
sequence and is DQPSK encoded for 5.5 and 11Mbps. This
will take the form of rotating the whole symbol by the
appropriate amount relative to the phase of the preceding
symbol. Note that the last chip of the symbol defined above
is the chip that indicates the symbol’s reference phase.
For the 5.5Mbps CCK mode, the output of the scrambler is
partitioned into nibbles. The first two bits are encoded as
differential symbol phase modulation in accordance with Table
8. All odd numbered symbols of the MPDU are given an extra
180 degree ( ) rotation in addition to the standard DQPSK
modulation as shown in the table. The symbols of the MPDU
shall be numbered starting with “0” for the first symbol for the
purposes of determining odd and even symbols. That is, the
MPDU starts on an even numbered symbol. The last data dibit
(d2 and d3) CCK encodes the chips as specified in Table 9.
This table is derived from the CCK formula above by setting 2
= (d2*pi)+ pi/2, 3 = 0, and 4 = d3*pi. In Table 9 d2 and d3 are
in the order shown and the complex chips are shown LSB to
MSB (left to right) with LSB transmitted first.
At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes the phase 1 based on
DQPSK. The DQPSK encoder is specified in Table 8 above.
The phase change for 1 is relative to the phase 1 of the
preceding symbol. In the case of rate change, the phase
change for 1 is relative to the phase 1 of the preceding
CCK symbol. All odd numbered symbols of the MPDU are
DIBIT PATTERN (d(0), d(1))
d2, d3
d(0) IS FIRST IN TIME
00
01
10
11
TABLE 9. 5.5Mbps CCK ENCODING TABLE
-1j
-1j
1j
1j
00
01
11
10
TABLE 8. DQPSK ENCODING TABLE
-1
-1
1
1
-1j
-1j
1j
1j
EVEN SYMBOLS
PHASE CHANGE
22
3 /2 (- /2)
-1
-1
1
1
CHIPS
(+j
0
/2
-1j
-1j
1j
1j
1
1
1
1
PHASE CHANGE
ODD SYMBOLS
3 /2 (- /2)
(+j )
-1j
-1j
1j
1j
0
/2
1
1
1
1
ISL3873B
given an extra 180 degree ( ) rotation in accordance with the
DQPSK modulation as shown in Table 8. Symbol numbering
starts with “0” for the first symbol of the MPDU.
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode 2, 3,
and 4 respectively based on QPSK as specified in Table
10. Note that this table is binary, not grey, coded.
Transmit Filter Description
To minimize the requirements on the analog transmit filtering,
the transmit section shown in Figure 17 has an output digital
filter. This filter is a Finite Impulse Response (FIR) style filter
whose passband shape is set by tap coefficients. This filter
shapes the spectrum to meet the radio spectral mask
requirements while minimizing the peak to average amplitude
on the output. To meet the particular spread spectrum
processing gain regulatory requirements in Japan on channel
14, an extra FIR filter shape has been included that has a
wider main lobe. This increases the 90% power bandwidth
from about 11MHz to 14MHz. It has the unavoidable side
effect of increasing the amplitude modulation, so the available
transmit power is compromised by 2dB when using this filter
(CR 11 bit 5).
TX Power Control
The transmitter power can be controlled via two registers.
The first register, CR58, contains the results of power
measurements digitized by the ISL3873B. By comparing this
measurement to what is needed for transmit power, a
determination is made whether to raise or lower the transmit
power. It does this by writing the power level desired to
register CR31.
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
The Clear Channel Assessment (CCA) circuit implements the
carrier sense portion of a Carrier Sense Multiple Access
(CSMA) networking scheme. The Clear Channel Assessment
(CCA) monitors the environment to determine when it is clear
to transmit. The CCA circuit in the ISL3873B can be
programmed to be a function of RSSI (energy detected on the
channel), CS1, SQ1, or various combinations. The CCA is
used by the Media Access Controller (MAC) in the ISL3873B.
The MAC decides on transmission based on traffic to send
and the CCA indication. The CCA indication can be ignored,
allowing transmissions independent of any channel
conditions. The CCA in combination with the visibility of the
various internal parameters (i.e., Energy detection
DIBIT PATTERN (d(i), d(i+1))
d(i) IS FIRST IN TIME
TABLE 10. QPSK ENCODING TABLE
00
01
10
11
3 /2 (- /2)
PHASE
0
/2