CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 25

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
5.3
When NSEs are cascaded using multiple Ayama 10000A devices, the SADR, CE_L, and WE_L (three-state signals) are all tied
together. In order to eliminate external pull-up and pull-downs, one device in a bank is designated the default driver. For non-
search or non-learn cycles (see Subsection 6.6, “Learn Command”) or Search cycles with a global miss, the SADR, CE_L, and
WE_L signals are driven by the device with the LRAM bit set. It is important that only one device in a bank of cascaded NSEs
have this bit set. Failure to do so will cause contention on the SADR, CE_L, and WE_L, and can potentially cause damage to the
device(s).
Similarly, when NSEs using multiple Ayama 10000A devices are cascaded, SSF and SSV (also three-state signals) are tied
together. In order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. For non-
search cycles or Search cycles with a global miss, the SSF and SSV signals are driven by the device with the LDEV bit set. It is
important that only one device in a bank of cascaded NSEs have this bit set. Failure to do so will cause contention on the SSV
and SSF, and can potentially cause damage to the device(s).
5.4
Table 5-6 provides an overview of all the Ayama 10000A internal registers. Each register is 72 bits wide. The Ayama 10000A
contains sixteen pairs of comparand storage registers, sixteen pairs of global mask registers, eight Search status index registers,
sixteen Search control parameters registers, sixteen Search result registers and one each of command, information, burst Read,
burst Write, next-free address register, partition configuration, hardware and parity control registers. Each of the blocks in the
NSE device (128/64/32 2Kx72 blocks in CYNSE10512A/256A/128A respectively) also has one each of Block Mini-Key, Block
Priority, Block Parity and Block Next-free Address registers. There are also four Block Priority Register Aliases registers for each
Block Priority register that allows an alternative way to update the Block Priority registers. The registers are presented in
ascending address order. Each register group is then described in the following subsections. Reserved fields in the registers are
read as 0s. When writing to the registers, all Reserved fields must be written with 0s, unless specified otherwise in the field’s
description.
Table 5-6. List of Internal Registers
(decimal)
Address
96–111
32–47
48–55
0–31
56
57
58
59
60
61
62
63
Output Signals Default Driver/Last Device Designation (LRAM and LDEV)
Registers
(Hexadecimal) Abbreviation
000 - 01F
020 - 02F
060 - 06F
030 - 037
Address
03A
03B
03C
03D
03E
038
039
03F
HARDWARE
COMMAND
WBURREG
CMPR0–15
RBURREG
GMR8–15
GMR0–7
CONFIG
SSR0–7
PARITY
INFO
NFA
CONFIDENTIAL
(Read/Write)
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
Comparand Register. Sixteen CMPR pairs (144 bits per pair) that
store comparands from the DQ bus during a Search operation for
later use with the Learn command. See Section 5.4.1.
Global Mask Register. Sixteen GMR pairs (144 bits per pair) used
for global mask bits on the DQ bus for all commands. See
Section 5.4.2.
Search Successful Register. These registers store the result of
Search operations. See Section 5.4.3.
Command Register. This register contains control fields that
determine how the NSE operates. See Section 5.4.4.
Information Register. This Read-only register contains static infor-
mation about the NSE device. See Section 5.4.5.
Burst-Read Register. This register contains the starting address
and count for a Read Burst operation. See Section 5.4.6.
Burst-Write Register. This register contains the starting address
and count for a Write Burst operation. See Section 5.4.7.
Next-free Address Register. This register contains the index of
the next-free entry when the device is in the Non-Enhanced mode
(Enhanced mode uses SRR registers to store the next-free entry
information). See Section 5.4.8.
Partition Configuration Register. This register contains the
partition type bits when the NSE device operates in the Non-
Enhanced mode. It is not used in the Enhanced mode. See
Section 5.4.9.
Hardware Register. This register contains I/O drive strength
settings. See Section 5.4.10.
Parity Control Register. This register contains the control and
address for parity checking of the Core and registers. See
Section 5.4.11.
Description
CYNSE10512A
CYNSE10256A
CYNSE10128A
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