CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 52

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
6.3
In both the Non-Enhanced and Enhanced mode, the Read command can be issued to read data from the data array, mask array,
NSE-associated SRAMs or internal registers. The Read can be a single or burst Read (Table 6-5). Burst Read can only be issued
for accesses to the data or mask array locations. SRAM Read operation is covered in Section 6.7.1 to Section 6.7.3. In the
Enhanced mode, the Read command is also used to issue the Read Parity command, which is issued to perform parity check
on the data and mask array entries.
Read is a blocking operation and must be completed before the next operation can be issued.
Table 6-5. Single/Burst Read Command Parameters
6.3.1
A single Read operation lasts six cycles (CLK1X) with the data driven out by the NSE on cycle 5 as illustrated in Figure 6-1.
Read operation sequence:
At the termination of cycle 6, the selected device releases the ACK line to a three-state condition. The Read instruction is complete
and the next operation can begin.
• Cycle 1: The host ASIC applies the Read instruction on CMD[1:0] (CMD[2] = 0) using CMDV = 1, and the DQ bus supplies
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive the DQ[71:0] bus and drives the ACK signal from Z to LOW.
• Cycle 5: The selected device drives the Read data from the addressed location on the DQ[71:0] bus, and drives the ACK
• Cycle 6: The selected device floats the DQ[71:0] to a three-state condition and drives the ACK signal LOW.
CMD Parameter
the address. The host ASIC selects the Ayama 10000A device for which ID[4:0] matches the DQ[25:21] lines. If DQ[25:21] =
11111, the host ASIC selects the Ayama 10000A with the LDEV bit set. The host ASIC also supplies SADR[25:23] for
CYNSE10512A, SADR[24:22] for CYNSE10256A, SADR[23:21] for CYNSE10128A on CMD[8:6] in cycle A of the Read
instruction if the Read is directed to the external SRAM.
signal HIGH.
CMD[2]
Read Command
Single Read
0
1
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
Read Command
CMDV
ACK
Single Read
Burst Read
DQ
Figure 6-1. Single-Location Read Cycle Timing
Reads a single location of the data array, mask array, NSE-associated SRAM or internal
registers. All access information is applied on the DQ bus.
Reads a block of locations from the data or mask array as a burst. RBURREG specifies
the starting address and the length of the data transfer from the data or mask array; it
also auto-increments the address for each access. All other access information is
applied on the DQ bus.
CONFIDENTIAL
cycle
A
Address
1
Read
B
cycle
2
cycle
3
cycle
4
Description
0
cycle
5
Data
cycle
6
CYNSE10512A
CYNSE10256A
CYNSE10128A
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