CYNSE10512A-133FGC Cypress Semiconductor Corp, CYNSE10512A-133FGC Datasheet - Page 61

• Manufacturer Part Number: CYNSE10512A-133FGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE10512A-133FGC

• Operating Supply Voltage (typ): 1.2V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02110 Rev. *B
Notes.
The latency of the Search from command to SRAM access cycle is 5 for a single device (or up to eight devices) configuration in
the table (TLSZ[1:0] = 01). SSV and SSF also shift further to the right for different values of HLAT, as specified in Table 6-8.
Figure 6-9 shows a multiwidth configuration when multisearch is enabled using CYNSE10512A as an example.
The NES field in the Block Mini-Key Register (BMR) should be configured as follows:
6.5.3
The hardware diagram of the Search subsystem of up to eight devices is shown in Figure 6-10. The MultiSearch Mode (MSE) bit
in the Command Register must be set LOW to perform single-search. The following are the rest of the parameters programmed
into the eight devices.
1. For 72-bit leading + 72-bit trailing MultiSearches, the host ASIC can supply different 72-bit data on DQ[71:0] during both cycles
2. For all other Multisearch commands that contain a 72-bit trailing search, you must pay special attention to which part of the
3. For all other Multisearches, the N-bit search key used for the N-bit trailing search is simply the last N-bits presented on the
4. GMR and CPR selection also deserve special attention, please see Section 5.1.2.4 for details.
5. A matching entry from each array that satisfies the Soft Priority and Mini-Key scheme will be the winning entries, and their
6. Reading CMPR registers after Multisearches: You can only do this if your leading and trailing searches are of same width.
7. Learning from CMPR is only supported if your leading and trailing searches are of same width.
• Cycle B:
• For the first 32 blocks in the data array, NES = 00 (binary) for 72-bit table width. For the next 16 blocks, NES = 01 (binary) for
• Setting NES = 00 (binary) for the next 32 blocks will configure those blocks to be 72-bit table in array 1. Setting NES = 01
• In Non-Enhanced Mode, first seven devices (devices 0–6) must reset all bits of the CFG field in Configuration register to zeroes.
A and B to be compared with the tables in array 0 and 1 of the data array. The even and odd pairs of GMRs selected for the
comparison need not be programmed with the same value.
entire search key is used for the 72-bit trailing search. An example of this situation is illustrated in M-search 2 and M-search
3 in Figure 6-7. M-search 2 is a 144-bit leading search on Array 0 plus a 72-bit trailing search on Array 1. Notice that the Y2
portion of the entire key is used during the 72-bit search. Different behavior is observed for a leading search in Array 1 instead
of Array 0. M-search 3 is a 288-bit leading search on Array 1 plus a 72-bit trailing search on Array 0. In this example, Z3 is
used as the 72-bit key for the trailing 72-bit search. The difference between M-search 2 and M-search 3 is the trailing 72-bit
search (Array 0 and Array 1 respectively). This behavior is summarized as follows:
DQ bus when the Multisearch command is issued.
location addresses La and Lb, will be driven as part of the SRAM address on the SADR[N:0] lines (see Section 6.7, “SRAM
PIO Access,” on page 113), N = 25 for CYNSE10512A, 24 for CYNSE10256A, 23 for CYNSE10128A.
144-bit table width. For the following 16 blocks, NES = 10 (binary) for 288-bit table width. These will configure the tables in array 0.
(binary) for the next 16 blocks will configure those blocks to be 144-bit table. Setting the final 16 blocks’ NES field will configure
those blocks to be 288-bit table.
In Enhanced Mode, these devices should have the NES field of each block within a device configured to 00 for 72-bit table
width. TLSZ = 01 (binary), HLAT = 010 (binary), LRAM = 0 (binary), and LDEV = 0 (binary) for both modes.
— DQ Bus: At the same time in cycle A, DQ[71:0] must be driven with the 72-bit data to be compared.
— Command Bus: The host ASIC continues to drive CMDV HIGH and to apply Search command CMD[1:0] = “10”. CMD[5:2]
— DQ Bus: The DQ[71:0] continues to carry the search key to be compared.
•
•
72-bit trailing search on Array 0: Data on DQ during the last Cycle A of the entire Search command will be used as search key
72-bit trailing search on Array 1: Data on DQ during the last Cycle B of the entire Search command will be used as search key
must now be driven by the index of the comparand register pair for storing the search key presented on the DQ bus during
cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the
matching entry and hit flag (see page 27 for a description of SSR[0:7]). CMD[10:9] are don’t cares for this cycle.
72-bit Single Search for 1 device or cascade up to eight devices
Figure 6-9. Multiwidth Configurations Using CYNSE10512A as an Example
64K
16K
8K
CONFIDENTIAL
72
144
Upper half
(Array 0)
288
64K
16K
8K
72
144
Lower half
(Array 1)
288
CYNSE10512A
CYNSE10256A
CYNSE10128A
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