SCANSTA111SM National Semiconductor, SCANSTA111SM Datasheet - Page 19

• Manufacturer Part Number: SCANSTA111SM
• Manufacturer: National Semiconductor

Specifications of SCANSTA111SM

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: FBGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

Special Features
TRANSPARENT MODE
While this mode is activated, the selected LSP n ports will
follow the backplane ports. TRST
TRST
buffered version of TMS
TDI
TRIST
Shift-DR or Shift-IR states. The unselected LSPs are placed
in the PARKTLR state, and their clocks are gated after 512
TCK
Transparent Mode is controlled by 8 new instructions,
TRANSPARENT0 through TRANSPARENT7. Transparent
Mode overrides any other active mode. When one of the
transparent mode instruction is shifted into the instruction
register and the tap controller goes through the UPDATE-IR
state, TRST
the targets connected to the LSP
state. Then as the 'STA111 state machine goes into the RTI
state, all of the LSP
This is identical to the method that is typically used to unpark
an LSP. The 'STA111 will remain in this mode until a TRST
is asserted or a power cycle forces a reset. Once in the Trans-
parent Mode, the 'STA111 will not be able to be reset by a 5
TMS high reset.
The sequence of operations to use Transparent Mode on an
LSP are as follows (example uses LSP
1.
2.
NOTE: Transparent Mode will persist until the 'STA111 is re-
set using TRST
structions will not work in this mode.
BIST SUPPORT
The sequence of instructions to run BIST testing on a parked
SCANSTA111 port is as follows:
1.
2.
3.
4.
5.
B
B
IR-Scan the 'STA111 address into the instruction register
(address a 'STA111).
IR-Scan the TRANSPARENT0 instruction to enable
Transparent Mode on LSP
enabled when the TAP enters the RTI state at the end of
this shift operation (TRST
become buffered versions of TRST
TCK
Pre-load the Boundary register of the device under test
if needed.
Issue the CNTRSEL instruction and initialize (load) the
TCK counter to 00000000 Hex. Note that the TCK
counter is initialized to 00000000 Hex upon Test-Logic-
Reset, so this step may not be necessary.
Issue the CNTRON instruction to the 'STA111, to enable
the TCK counter.
Shift the PARKRTI instruction into the 'STA111
instruction register and BIST instruction into the
instruction register of the device under test. With the
counter on (at terminal count) and the LSP parked, the
local TCK is gated.
Issue the CNTRSEL instruction to the 'STA111.
and TDO
B
clock cycles.
n
, TCK
are asserted when the state machine is in either the
B
and TDO
n
n
will go high, and TMS
B
is a buffered version of TCK
B
is a buffered version of TDI
. The GOTOWAIT and SOFTRESET in-
n
B
signals will follow the back-plane signals.
becomes a buffered version of TDI
B
, TDO
0
0
, TDO
. Transparent Mode is
n
n
n
n
is a buffered version of
will go low. This will force
ports to go into the RTI
is a buffered version of
0
, TMS
0
B
):
, TDI
0
n
and TCK
B
B
. TRIST
, TMS
, TMS
B
n
and
B
0
is a
0
and
).
B
19
6.
7.
8.
9.
RESET
Reset operations can be performed at three levels. The high-
est level resets all 'STA111 registers and all of the local scan
chains of selected and unselected 'STA111s. This Level 1 re-
set is performed whenever the 'STA111 TAP Controller enters
the Test-Logic-Reset state. Test-Logic-Reset can be entered
synchronously by forcing TMS
TCK
A Level 1 reset forces all 'STA111s into the Wait-For-Ad-
dress state, parks all local scan chains in the Test-Logic-
Reset state, and initializes all 'STA111 registers.
The SOFTRESET instruction is provided to perform a Level
2 reset of all LSP's of selected 'STA111s. SOFTRESET
forces all TMS
TAP Controllers in the Test-Logic-Reset state within five (5)
TCK
The third level of reset is the resetting of individual local ports.
An individual LSP can be reset by parking the port in the Test-
Logic-Reset state via the PARKTLR instruction. To reset an
individual LSP that is parked in one of the other parked states,
the LSP must first be unparked via the UNPARK instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of the
four TAP Controller states: Test-Logic-Reset, Run-Test/Idle,
Pause-DR, or Pause-IR. The 'STA111 is able to park a local
chain by controlling the local Test Mode Select outputs (TMS
(0-2)
Test-Logic-Reset state, and forced low for parking in Run-
Test/Idle, Pause-IR, or Pause-DR states. Local chain access
is achieved by issuing the UNPARK instruction. The LSPs do
not become unparked until the 'STA111 TAP Controller is se-
quenced through a specified synchronization state. Synchro-
nization occurs in the Run-Test/Idle state for LSPs parked in
Test-Logic-Reset or Run-Test/Idle; and in the Pause-DR or
Pause-IR state for ports parked in Pause-DR or Pause-IR,
respectively.
Figure 11
nization of a local chain that was parked in the Test-Logic-
Reset state. Once the UNPARK instruction is received in the
instruction register, the LSPC forces TMS
edge of TCK
) (see
Load the TCK counter (Shift the 32-bit value representing
the number of TCK
operation into the TCK counter register). The Self test will
begin on the rising edge of TCK
DR TAP controller state.
Bit 7 of Mode Register
status of the TCK counter, (MODESEL instruction
followed by a Shift-DR). Bit 7 logic 0 means the counter
has not reached terminal count, logic 1 means that the
counter has reached terminal count and the BIST
operation has completed.
Execute the CNTROFF instruction.
Unpark the LSP and scan out the result of the BIST
operation
B
B
pulses, or asynchronously by asserting the TRST
cycles.
Figure
and
B
n
.
Figure 12
signals high, placing the corresponding local
4). TMS
n
cycles needed to execute the BIST
n
show the waveforms for synchro-
0
is forced high for parking in the
can be scanned to check the
B
high for at least five (5)
B
following the Update-
n
low on the falling
www.national.com
B
pin.