ML610Q408-NNNTBZ03A7 Rohm Semiconductor, ML610Q408-NNNTBZ03A7 Datasheet
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ML610Q408-NNNTBZ03A7 Summary of contents
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... ML610Q407/ML610Q408/ML610Q409 User’s Manual FEUL610Q409-01 Issue Date: Nov. 7, 2010 ...
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...
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... IDEU8 User’s Manual Description on the integrated development environment uEASE User’s Manual Description on the on-chip debug tool uEASE. uEASE connection Manual for ML610Q407/ML610Q408/ML610Q409 Description about the connection between uEASE and . ML610Q408/ ML610Q409 FWuEASE Flash Writer Host Program User’s Manual Description on the Flash Writer host program ...
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Classification Notation ♦ Numeric value xxh, xxH xxb ♦ Unit word, W byte, B nibble, N maga-, M kilo-, K kilo-, k milli-, m micro-, µ nano-, n second, s (lower case) ♦ Terminology “H” level, “1” level “L” level, ...
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... Block Diagram of ML610Q407/ML610Q408/ML610Q409.............................................................................. 1-4 1.3 Pins .............................................................................................................................................................................. 1-5 1.3.1 Pin Layout............................................................................................................................................................. 1-5 1.3.1.1 Pin Layout of ML610Q407 TQFP Package ......................................................................................................................... 1-5 1.3.1.2 Pin Layout of ML610Q408 TQFP Package ......................................................................................................................... 1-6 1.3.1.3 Pin Layout of ML610Q409 TQFP Package ......................................................................................................................... 1-7 1.3.1.4 Pin Layout of ML610Q407 Chip.......................................................................................................................................... 1-8 1.3.1.5 Pin Layout of ML610Q408 Chip.......................................................................................................................................... 1-9 1 ...
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... ML610Q407/ML610Q408/ML610Q409 User’s Manual Contents Chapter 4 4. MCU Control Function......................................................................................................................................................... 4-1 4.1 Overview ...................................................................................................................................................................... 4-1 4.1.1 Features................................................................................................................................................................. 4-1 4.1.2 Configuration........................................................................................................................................................ 4-1 4.2 Description of Registers ............................................................................................................................................... 4-2 4.2.1 List of Registers .................................................................................................................................................... 4-2 4.2.2 Stop Code Acceptor (STPACP) ............................................................................................................................ 4-3 4.2.3 Standby Control Register (SBYCON) .................................................................................................................. 4-4 4.2.4 Block Control Register 0 (BLKCON0) ................................................................................................................ 4-5 4 ...
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Chapter 6 6. Clock Generation Circuit...................................................................................................................................................... 6-1 6.1 Overview ...................................................................................................................................................................... 6-1 6.1.1 Features................................................................................................................................................................. 6-1 6.1.2 Configuration........................................................................................................................................................ 6-1 6.1.3 List of Pins............................................................................................................................................................ 6-2 6.2 Description of Registers ............................................................................................................................................... 6-2 6.2.1 List of Registers .................................................................................................................................................... 6-2 6.2.2 Frequency Control Register 0 (FCON0)............................................................................................................... ...
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... ML610Q407/ML610Q408/ML610Q409 User’s Manual Contents 8.2.6 Capture Time Base Data Register (CAPTB)......................................................................................................... 8-7 8.3 Description of Operation .............................................................................................................................................. 8-8 Chapter 9 9. Timer .................................................................................................................................................................................... 9-1 9.1 Overview ...................................................................................................................................................................... 9-1 9.1.1 Features................................................................................................................................................................. 9-1 9.1.2 Configuration........................................................................................................................................................ 9-1 9.1.3 List of Pins............................................................................................................................................................ 9-2 9.2 Description of Registers ............................................................................................................................................... 9-3 9.2.1 List of Registers .................................................................................................................................................... 9-3 9 ...
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PWM0 Control Register 1 (PW0CON1) .......................................................................................................... 10-7 10.3 Description of Operation .......................................................................................................................................... 10-8 10.4 Specifying port registers ........................................................................................................................................ 10-10 10.4.1 Functioning the P43 pin (PWM0) as the PWM output................................................................................... 10-10 10.4.2 Functioning the P24 pin (PWM0) as the PWM ...
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... ML610Q407/ML610Q408/ML610Q409 User’s Manual Contents SSIO1/ ”Slave mode” ................................................................................................................................................... 12-20 12.4.7 Functioning P56 (SOUT1: Output), P55 (SCK1: Input/Output), and P54 (SIN1: Input) as the SSIO1/ “Master mode”.............................................................................................................................................................. 12-21 12.4.8 Functioning P56 (SOUT1: Output), P55 (SCK1: Input/Output), and P54 (SIN1: Input) as the SSIO1/ ” ...
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Features............................................................................................................................................................... 15-1 15.1.2 Configuration...................................................................................................................................................... 15-1 15.1.3 List of Pins.......................................................................................................................................................... 15-1 15.2 Description of Registers ............................................................................................................................................. 15-2 15.2.1 List of Registers .................................................................................................................................................. 15-2 15.2.2 Port 2 Data Register (P2D) ................................................................................................................................. 15-3 15.2.3 Port 2 Control Registers 0, 1 (P2CON0, P2CON1)............................................................................................ ...
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... ML610Q407/ML610Q408/ML610Q409 User’s Manual Contents 18.2.2 Port 5 Data Register (P5D) ................................................................................................................................. 18-3 18.2.3 Port 5 Direction Register (P5DIR)...................................................................................................................... 18-4 18.2.4 Port 5 Control Registers 0 and 1 (P5CON0 and P5CON1) ................................................................................ 18-5 18.2.5 Port 5 Mode Register 0 and 1 (P5MOD0 and P5MOD1)................................................................................... 18-7 18.2.6 Port 5 Interrupt mode Register (P5ISEL) ........................................................................................................... 18-9 18 ...
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List of Pins.......................................................................................................................................................... 21-2 21.2 Description of Registers ............................................................................................................................................. 21-3 21.2.1 List of Registers .................................................................................................................................................. 21-3 21.2.2 RC-ADC Counter A Registers (RADCA0–1)..................................................................................................... 21-4 21.2.3 RC-ADC Counter B Registers (RADCB0–1)..................................................................................................... 21-5 21.2.4 RC-ADC Mode Register (RADMOD) ............................................................................................................... 21-6 21.2.5 RC-ADC ...
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... ML610Q407/ML610Q408/ML610Q409 User’s Manual Contents Chapter 25 25. M ask ROM Version Emulation Function ....................................................................................................................... 25-1 25.1 Overview .................................................................................................................................................................. 25-1 25.2 Method of Connecting to On-Chip Debug Emulator................................................................................................ 25-1 25.3 Notice for the software Program Development ........................................................................................................ 25-2 25.3.1 Notice for the Mask ROM Version Mode setting data ........................................................................................ 25-2 25 ...
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ML610407/ML610408/ML610409 User’s Manual Contents –10 Contents ...
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Chapter 1 Overview ...
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... MTP version implements the mask ROM-equivalent low-voltage operation (1.2V or higher) and low-power consumption (typically 5uA at low-speed operation), enabling volume production by the MTP version. For industrial use, ML610Q407P/ML610Q408P/ML610Q409P with the extended operating ambient temperature ranging from -40°C to 85°C are available. ...
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... ML610Q407 145 dots (select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2 commons) ML610Q408 165 dots (select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons) ML610Q409 185 dots (select among 37 segments x 5 commons, 38 segments x 4 commons, 39 ...
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... ROM code number (xxx of the blank product is NNN) Q: MTP version P: Wide range temperature version (P version) WA: Chip (Die) TBZ03A: TQFP Guaranteed Operation Range − Operating temperature: -20°C to +70°C (P version: -40°C to +85°C) − Operating voltage 1.25V to 3.6V DD ML610Q407/ML610Q408/ML610Q409 User's Manual 1-3 Chapter 1 Overview ...
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... Select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2 commons with the register “*3”: Select among 37 segments x 5 commons, 38 segments x 4 commons, 39 segments x 3 commons, and 40 segments x 2 commons with the register Figure 1-1 Block Diagram of ML610Q407/ML610Q408/ML610Q409 CPU (nX-U8/100) ELR1−3 ECSR1−3 GREG 0− ...
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... P35 92 P57 93 P56 94 P55 95 P54 96 P53 (NC) 99 (NC) 100 (NC): No Connection Note: The assignment of the pads P30 to P35 are not in order. ML610Q407/ML610Q408/ML610Q409 User's Manual Figure 1-2 Pin Layout of ML610Q407 Package 1-5 Chapter 1 Overview (NC) 50 (NC SEG17 47 SEG16 SEG15 46 SEG14 45 SEG13 44 SEG12 43 42 SEG11 ...
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... P33 91 P35 92 P57 93 P56 94 P55 95 P54 96 P53 (NC) 99 (NC) 100 (NC): No Connection Note: The assignment of the pads P30 to P35 are not in order. Figure 1-3 Pin Layout of ML610Q408 Package 1-6 50 (NC) (NC) 49 SEG17 48 SEG16 47 SEG15 46 45 SEG14 44 SEG13 SEG12 43 SEG11 42 41 SEG10 SEG9 40 ...
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... P30 87 P31 88 P34 89 P32 90 P33 91 P35 92 P57 93 P56 94 P55 95 P54 96 P53 (NC) 99 (NC) 100 (NC): No Connection Note: The assignment of the pads P30 to P35 are not in order. Figure 1-4 Pin Layout of ML610Q409 Package ML610Q407/ML610Q408/ML610Q409 User's Manual 1-7 Chapter 1 Overview (NC) (NC) SEG17 SEG16 SEG15 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 1 Overview 1.3.1.4 Pin Layout of ML610Q407 Chip P20 68 P21 69 P22 70 P24 71 P00 72 P01 73 P02 74 P03 75 P04 76 P30 77 P31 78 P34 79 P32 80 P33 81 P35 82 P57 83 P56 84 P55 85 P54 86 P53 Note: The assignment of the pads P30 to P35 are not in order. 2.27mm Chip size: 2.27 mm × ...
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... P53 Note: The assignment of the pads P30 to P35 are not in order. Figure 1-6 Dimensions of ML610Q408 Chip ML610Q407/ML610Q408/ML610Q409 User's Manual 2.27mm Chip size: 2.27 mm × 2.23 mm PAD count: 88 pins Minimum PAD pitch: 80μm PAD aperture: 70μm×70μm Chip thickness: 350μm ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 1 Overview 1.3.1.6 Pin Layout of ML610Q409 Chip P20 68 P21 69 P22 70 P24 71 P00 72 P01 73 P02 74 P03 75 P04 76 P30 77 P31 78 P34 79 P32 80 P33 81 P35 82 P57 83 P56 84 P55 85 P54 86 P53 Note: The assignment of the pads P30 to P35 are not in order. 2.27mm Chip size: 2.27 mm × ...
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... Pad Coordinates of ML610Q407/ML610Q408/M610Q409 Chip Table 1-1 Pad Coordinates of ML610Q407/ML610Q408/ML610Q409 ML610Q407/8/9 PAD Pad No. Name X (μm) 1 P52 -853 2 P51 -773 3 P50 -693 4 P40 -613 5 P41 -533 6 P42 -453 7 P43 -373 8 P44 -293 9 P45 -213 10 P46 -133 11 P47 - 107 187 DDL 15 XT0 267 ...
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Chapter 1 Overview 1.3.2 List of Pins Primary function PIN PAD No. No. Pin name I/O ⎯ 14,77 13,67 Vss ⎯ ⎯ DDL ⎯ ⎯ L1 ...
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... P55/EXI8 I/O External interrupt Input/output port P56/EXI8 I/O External interrupt Input/output port P57/EXI8 I/O External interrupt ML610Q407/ML610Q408/ML610Q409 User's Manual Secondary function or Tertiary function Secondary Function Pin name /Tertiary Secondary Tertiary Secondary Tertiary Secondary Tertiary SOUT0 Secondary Tertiary PWM0 Secondary Tertiary ...
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... Pin for ML610Q407/ML610Q408 Pin for ML610Q409 Pin for ML610Q407 Pin for ML610Q408/ML610Q409 Secondary/ Function LCD common pin LCD common pin LCD common/segment pin LCD common/segment pin LCD common/segment pin LCD segment pin LCD segment pin LCD segment pin LCD segment pin ...
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... P60 to P63 I/O General-purpose input/output port. Incorporated only into ML610Q407/8, and not into ML610Q409. P64 to P67 I/O General-purpose input/output port. Incorporated only into ML610Q407, and not into ML610Q408/ ML610Q409. ML610Q407/ML610Q408/ML610Q409 User's Manual Description are connected across this pin and V SS ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 1 Overview Pin name I/O UART TXD0 O UART data output pin. This pin is used as the secondary function of the P43 pin. RXD0 I UART data input pin. This pin is used as the secondary function of the P42 or the primary function of the P02 pin. ...
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... Segment output pin. The SEG0, SEG1, and SEG2 pins are for SEG23 switching the register setting with the COM2, COM3, and COM4. SEG24 to O Segment output pin. Incorporated into ML610Q408/ML610Q409, SEG27 not into ML610Q407. SEG28 to O Segment output pin. Incorporated into ML610Q409, not into SEG31 ML610Q407/ML610Q408 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 1 Overview I/O Pin name Test TEST0 I/O Pin for testing. A pull-down resistor is internally connected. TEST1_N I Pin for testing. A pull-up resistor is internally connected. Power supply V — Negative power supply pin — Positive power supply pin — Positive power supply pin (internally generated) for internal logic. ...
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... It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. ML610Q407/ML610Q408/ML610Q409 User's Manual Table 1-2 Termination of Unused Pins Recommended pin handling ...
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CPU and Memory Space Chapter 2 ...
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CPU and Memory Space 2.1 Overview This LSI includes 8-bit CPU nX-U8/100 and the memory model is SMALL model. For details of the CPU nX-U8/100, see “nX-U8/100 Core Instruction Manual”. 2.2 Program Memory Space The program memory space is ...
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Chapter 2 CPU 2.3 Data Memory Space The data memory space of this LSI consists of the ROM window area, 1KByte RAM area, and SFR area of Segment 0. The data memory has the 8-bit length and is specified by ...
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Instruction Length The length of an instruction is 16 bits. 2.5 Data Type The data types supported include byte (8 bits) and word (16 bits). Chapter 2 CPU and Memory Space 2-3 ...
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Chapter 2 CPU 2.6 Description of Registers 2.6.1 List of Registers Address 0F000H Data segment register Name Symbol (Byte) DSR 2-4 Symbol (Word) R/W Size — R/W 8 Initial value 00H ...
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Data Segment Register (DSR) Address: 0F000H Access: R/W Access size: 8-bit Initial value: 00H 7 DSR — R/W R/W Initial value 0 DSR is a special function register (SFR) to retain a data segment. Always use this register with ...
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Chapter 3 Reset Function ...
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... Reset when stop of the low-speed clock is detected WDT reset RSTAT : Reset status register Figure 3-1 Configuration of Reset Generation Circuit 3.1.3 List of Pins Pin name Input/output RESET_N I ML610Q407/ML610Q408/ML610Q409 User's Manual Function Reset input pin 3-1 Chapter 3 Reset Function RESET RSTAT Data bus ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 3 Reset Function 3.2 Description of Registers 3.2.1 List of Registers Address 0F001H Reset status register 3.2.2 Reset Status Register (RSTAT) Address: 0F001H Access: R/W Access size: 8-bit Initial value: Undefined 7 ⎯ RSTAT R/W R/W Initial value 0 RSTAT is a special function register (SFR) that indicates the causes by which the reset is generated. ...
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... In system reset mode, the contents of data memory and those of any SFR whose initial value is undefined are not initialized and are undefined. Initialize them by software. In system reset mode by the BRK instruction, no special function register (SFR) that has a fixed initial value is initialized either. Therefore initialize such an SFR by software. ML610Q407/ML610Q408/ML610Q409 User's Manual 3-3 Chapter 3 Reset Function ...
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MCU Control Function Chapter 4 ...
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MCU Control Function 4.1 Overview The operating states of this LSI are classified into the following 4 modes including system reset mode: (1) System reset mode (2) Program run mode (3) HALT Mode (4) STOP mode For system reset ...
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Chapter 4 MCU Control Function 4.2 Description of Registers 4.2.1 List of Registers Address Name 0F008H Stop code acceptor 0F009H Standby control register 0F028H Block control register 0 0F029H Block control register 1 0F02AH Block control register 2 0F02BH Block ...
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... During a system reset, the stop code acceptor is disabled. Note: The STOP code acceptor cannot be enabled on the condition of that both any interrupt enable flag and the corresponding interrupt request flag are “1”(An interrupt request occurrence with resetting MIE flag will have the condition). ML610Q407/ML610Q408/ML610Q409 User's Manual — ...
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Chapter 4 MCU Control Function 4.2.3 Standby Control Register (SBYCON) Address: 0F009H Access: W Access size: 8-bit Initial value: 00H 7 SBYCON — Initial value 0 SBYCON is a special function register (SFR) to control operating mode of ...
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... When using the function of the applicable block, ensure to reset the applicable flag of this block control register to "0" (enable operation). •See Chapter 9, “Timers” for detail about operation of Timer 0, Timer 1, Timer 2 and Timer 3. ML610Q407/ML610Q408/ML610Q409 User's Manual — ...
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... ML610Q40/7/ML610Q408/ML610Q409 User's Manual Chapter 4 MCU Control Function 4.2.5 Block Control Register 1 (BLKCON1) Address: 0F029H Access: R/W Access size: 8-bit Initial value: 00H 7 BLKCON1 — R/W R/W Initial value 0 BLKCON1 is a special function register (SFR) to control each block operation. [Description of Bits] • ...
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... When using the function of the applicable block, ensure to reset the applicable flag of this block control register to "0" (enable operation). •See Chapter 13, “UART” for detail about operation of UART. •See Chapter 12, “Synchronous Serial Port” for detail about operation of SSIO. ML610Q407/ML610Q408/ML610Q409 User's Manual — ...
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... ML610Q40/7/ML610Q408/ML610Q409 User's Manual Chapter 4 MCU Control Function 4.2.7 Block Control Register 3 (BLKCON3) Address: 0F02BH Access: R/W Access size: 8-bit Initial value: 00H 7 BLKCON3 — R/W R/W Initial value 0 BLKCON3 is a special function register (SFR) to control each block operation. [Description of Bits] • ...
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... Chapter 22, “LCD Driver” for detail about operation of LCD driver. •See Chapter 21, “RC Oscillation Type A/D Converter” for detail about operation of RC oscillation type A/D converter. ML610Q407/ML610Q408/ML610Q409 User's Manual — ...
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... ML610Q40/7/ML610Q408/ML610Q409 User's Manual Chapter 4 MCU Control Function 4.3 Description of Operation 4.3.1 Program Run Mode The program run mode is the state where the CPU executes instructions sequentially. At power-on reset, low-speed oscillation stop detect reset, WDT overflow reset, or RESET_N pin reset, the CPU executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after the system reset mode is released ...
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STOP mode The STOP mode is the state where low-speed oscillation and high-speed oscillation stop and the CPU and peripheral circuits stop the operation. When the stop code acceptor is enabled by writing “5nH”(n: an arbitrary value) and “0AnH”(n: ...
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Chapter 4 MCU Control Function 4.3.3.2 STOP Mode When CPU Operates with High-Speed Clock When the CPU is operating with the high-speed clock and the STP bit of SBYCON is set to “1” with the stop code acceptor enabled, the ...
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... ELEVEL bit is 2H, it indicates that the CPU is performing non-maskable interrupt processing. (ELEVEL is set during interrupt transition cycle.) •If the ELEVEL bit is 3H, it indicates that the CPU is performing interrupt processing specific to the emulator. This setting is not allowed in normal applications. ML610Q407/ML610Q408/ML610Q409 User's Manual Return operation from STOP/HALT mode 0 Not returned from STOP/HALT mode. ...
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Chapter 4 MCU Control Function 4.3.5 Block Control Function This LSI has a block control function, which resets and completely turns operating circuits of unused peripherals off to make even more reducing current consumption. For each block control register, the ...
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Chapter 5 Interrupt ...
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... Chapter 21, “RC Oscillation Type A/D Converter” 5.1.1 Features • Non-maskable interrupt source: 1 (Internal sources: 1) • Maskable interrupt sources: 27 (Internal sources: 14, External sources: 13) • Software interrupt (SWI): maximum 64 sources • External interrupts allow edge selection and sampling selection ML610Q407/ML610Q408/ML610Q409 User's Manual 5-1 Chapter 5 Interrupt ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2 Description of Registers 5.2.1 List of Registers Address Name 0F011H Interrupt enable register 1 0F012H Interrupt enable register 2 0F013H Interrupt enable register 3 0F014H Interrupt enable register 4 0F015H Interrupt enable register 5 0F016H Interrupt enable register 6 0F017H Interrupt enable register 7 ...
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... EP03 is the enable flag for the input port P03 pin interrupt (P03INT). EP03 0 Disabled (initial value) 1 Enabled • EP04 (bit 4) EP04 is the enable flag for the input port P04 pin interrupt (P04INT). EP04 0 Disabled (initial value) 1 Enabled ML610Q407/ML610Q408/ML610Q409 User's Manual — — EP04 EP03 R/W R Description ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.3 Interrupt Enable Register 2 (IE2) Address: 0F012H Access: R/W Access size: 8-bit Initial value: 00H 7 IE2 — R/W R/W Initial value 0 IE2 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE2 is not reset ...
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... ETM0 is the enable flag for the timer 0 interrupt (TM0INT). ETM0 0 Disabled (initial value) 1 Enabled • ETM1 (bit 1) ETM1 is the enable flag for the timer 1 interrupt (TM1INT). ETM1 0 Disabled (initial value) 1 Enabled ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W R Description Description 5-5 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.5 Interrupt Enable Register 4 (IE4) Address: 0F014H Access: R/W Access size: 8-bit Initial value: 00H 7 IE4 — R/W R/W Initial value 0 IE4 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE4 is not reset ...
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... ETM2 is the enable flag for the timer 2 interrupt (TM2INT). ETM2 0 Disabled (initial value) 1 Enabled • ETM3 (bit 5) ETM3 is the enable flag for the timer 3 interrupt (TM3INT). ETM3 0 Disabled (initial value) 1 Enabled ML610Q407/ML610Q408/ML610Q409 User's Manual — ETM3 ETM2 R/W R Description Description 5-7 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.7 Interrupt Enable Register 6 (IE6) Address: 0F016H Access: R/W Access size: 8-bit Initial value: 00H 7 IE6 E32H R/W R/W Initial value 0 IE6 is a special function register (SFR) to control enable/disable for each interrupt request. When an interrupt is accepted, the master interrupt enable flag (MIE) is set to “0”, but the corresponding flag of IE6 is not reset ...
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... E16H is the enable flag for the time base counter 16 Hz interrupt (T16HINT). E16H 0 Disabled (initial value) 1 Enabled • E2H (bit 3) E2H is the enable flag for the time base counter 2 Hz interrupt (T2HINT). E2H 0 Disabled (initial value) 1 Enabled ML610Q407/ML610Q408/ML610Q409 User's Manual — — — E2H R/W R Description ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.9 Interrupt Request Register 0 (IRQ0) Address: 0F018H Access: R/W Access size: 8-bit Initial value: 00H 7 IRQ0 — R/W R/W Initial value 0 IRQ0 is a special function register (SFR) to request an interrupt for each interrupt source. The watchdog timer interrupt (WDTINT non-maskable interrupt that do not depend on MIE. In this case, an interrupt is requested to the CPU regardless of the value of the Mask Interrupt Enable flag (MIE). Each IRQ0 request flag is set to “ ...
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... QP03 is the request flag for the input port P03 pin interrupt (P03INT). QP03 0 No request (initial value) 1 Request • QP04 (bit 4) QP04 is the request flag for the input port P04 pin interrupt (P04INT). QP04 0 No request (initial value) 1 Request ML610Q407/ML610Q408/ML610Q409 User's Manual — — QP04 QP03 R/W R Description ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ1 the interrupt enable register (IE1), the interrupt shift cycle starts after the next 1 instruction is executed. 5-12 ...
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... QP5 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ2 the interrupt enable register (IE2), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q407/ML610Q408/ML610Q409 User's Manual — — — QP5 R/W ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.12 Interrupt Request Register 3 (IRQ3) Address: 0F01BH Access: R/W Access size: 8-bit Initial value: 00H 7 IRQ3 — R/W R/W Initial value 0 IRQ3 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ3 request flag is set to “1” regardless of the IE3 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE3) is set to “ ...
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... QRA0 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ4 the interrupt enable register (IE4), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q407/ML610Q408/ML610Q409 User's Manual — QRAD — R/W R/W ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.14 Interrupt Request Register 5 (IRQ5) Address: 0F01DH Access: R/W Access size: 8-bit Initial value: 00H 7 IRQ3 — R/W R/W Initial value 0 IRQ5 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ5 request flag is set to “1” regardless of the IE3 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE5) is set to “ ...
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... Q32H 0 No request (initial value) 1 Request Note: When an interrupt is generated by the write instruction to the interrupt request register (IRQ6 the interrupt enable register (IE6), the interrupt shift cycle starts after the next 1 instruction is executed. ML610Q407/ML610Q408/ML610Q409 User's Manual — Q128H — R/W R/W ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.2.16 Interrupt Request Register 7 (IRQ7) Address: 0F01FH Access: R/W Access size: 8-bit Initial value: 00H 7 IRQ7 — R/W R/W Initial value 0 IRQ7 is a special function register (SFR) to request an interrupt for each interrupt source. Each IRQ7 request flag is set to “1” regardless of the IE7 and MIE values when an interrupt is generated. In this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE7) is set to “ ...
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... Note: - When multiple interrupts are generated concurrently, the interrupts are serviced according to this priority and processing of low-priority interrupts is pending. - Please define vector tables for all unused interrupts for fail safe. ML610Q407/ML610Q408/ML610Q409 User's Manual Table 5-1 Interrupt Sources Interrupt source Symbol WDTINT ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.3.1 Maskable Interrupt Processing When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the processing of program shifts to the interrupt destination. (1) Transfer the program counter (PC) to ELR1 (2) Transfer CSR to ECSR1 (3) Transfer PSW to EPSW1 (4) Set the MIE flag to “ ...
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... Specify “POP PC, PSW” instead of the RTI instruction to return the contents of the stack to PC and PSW. Example of description: Status A-1-1 Intrpt_A-1-1; ; A-1-1 state DI ; Disable interrupt : : : RTI ; Return PC from ELR ; Return PSW form EPSW ; End ML610Q407/ML610Q408/ML610Q409 User's Manual Example of description: Status A-1-2 Intrpt_A-1-2; ; Start PUSH ; Save ELR and EPSW at ELR,EPSW the beginning EI ; Enable interrupt : : : : : POP PC,PSW ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt A-2: When a subroutine is called by the program in executing an interrupt routine A-2-1: When multiple interrupts are disabled •Processing immediately after the start of interrupt routine execution Specify the “PUSH LR” instruction to save the subroutine return address in the stack. •Processing at the end of interrupt routine execution Specify “ ...
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... Start PUSH ; Save ELR, EPSW, and LR at ELR,EPSW,LR the beginning : : BL Sub_1 ; Call subroutine Sub_1 : POP PSW,PC,LR ; Return PC from the stack ; Return PSW from the stack ; Return LR from the stack ; End ML610Q407/ML610Q408/ML610Q409 User's Manual Sub_1 Return PC from LR ; End of subroutine 5-23 Chapter 5 Interrupt ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 5 Interrupt 5.3.5 Interrupt Disable State Even if the interrupt conditions are satisfied, an interrupt may not be accepted depending on the operating state. This is called an interrupt disabled state. See below for the interrupt disabled state and the handling of interrupts in this state. ...
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Clock Generation Circuit Chapter 6 ...
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... This LSI starts operation with the low-speed clock after power- system reset. At initialization by software, set the FCON0 or FCON1 register to switch the clock to a required one. Operation of this LSI is not guaranteed under a condition where a low-speed clock is not supplied. ML610Q407/ML610Q408/ML610Q409 User's Manual OSCLK Dividing selection ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 6 Clock Generation Circuit 6.1.3 List of Pins Input/o Pin name utput XT0 I Pin for connecting a crystal for low-speed clock. XT1 O Pin for connecting a crystal for low-speed clock. 6.2 Description of Registers 6.2.1 List of Registers Address Name 0F002H Frequency control register 0 ...
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... Note: Internal logic voltage ( changed by OSCM2 bit. V DDL 500kHz oscillation is selected. V Ensure to write this bit when the high-speed clock oscillator circuit stops oscillating (During FCON1 register's ENOSC bit is "0"). ML610Q407/ML610Q408/ML610Q409 User's Manual OUTC1 OUTC0 R/W R/W R/W 0 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 6 Clock Generation Circuit 6.2.3 Frequency Control Register 1 (FCON1) Address: 0F003H Access: R/W Access size: 8-bit Initial value: 00H 7 FCON1 — R/W R/W Initial value 0 FCON1 is a special function register (SFR) to control the high-speed clock generation circuit and to select system clock. ...
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... Note: Install a crystal as close to the LSI as possible and make sure that signals causing noise and power supply wiring are not near the crystal and its wiring. Note that oscillation may stop due to condensation. ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 6 Clock Generation Circuit V DDL ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 6 Clock Generation Circuit 6.3.1.2 Operation of Low-Speed Clock Generation Circuit The low-speed clock generation circuit is activated by the occurrence of power ON reset. After the power-on, it waits for the low-speed oscillation start time (T stabilization time (8192 counts). Then, the mode moves to the program run mode, the CPU starts operation, and at the same time the low-speed clock (LSCLK) is supplied to the peripheral circuits ...
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... OSCLK becomes the oscillation stopped state because the initial ENOSC value is "0". In the oscillation enabled (ENOSC set to "1") state, the OSCLK supply starts in 16 counts after the stop mode is released. ML610Q407/ML610Q408/ML610Q409 User's Manual V DDL ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 6 Clock Generation Circuit 6.3.2.2 Operation of High-Speed Clock Generation Circuit The high-speed clock generation circuit allows the start/stop control of oscillation by using the frequency control registers 0 and 1 (FCON0 and FCON1). Oscillation can be started by setting the ENOSC bit of FCON1 to "1" after selecting a high-speed oscillation frequency with FCON0 ...
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... If the system clock is switched from a low-speed clock to a high-speed clock before the high-speed clock (HSCLK) starts oscillation, the CPU becomes inactive until HSCLK starts clock supply to the peripheral circuits. ML610Q407/ML610Q408/ML610Q409 User's Manual Switches the system clock (high-speed clock to low-speed clock) Stops high-speed oscillation ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 6 Clock Generation Circuit 6.4 Specifying Port Registers To enable the clock output function, each related port register bit needs to be set. See Chapter 15, "Port 2" for detail about the port registers. 6.4.1 Functioning P21 (OUTCLK) as the high-speed clock output Set P21MD bit (bit1 of P2MOD register) to “ ...
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... Bit name Setting - value - : Bit that does not exist * : Bit not related to the low-speed clock function ** : Don’t care Note: P20 (Port output-only port and does not have the register to select the data direction(input or output). ML610Q407/ML610Q408/ML610Q409 User's Manual P2MOD register (Address: 0F214H ...
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Time Base Counter Chapter 7 ...
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... LTBR Write LTBR : Low-speed time base counter register LTBADJL : Low-speed time base counter frequency adjustment register LTBADJH : Low-speed time base counter frequency adjustment register Figure 7-1 Configuration of Low-Speed Time Base Counter (LTBC) ML610Q407/ML610Q408/ML610Q409 User's Manual LTBR 8bits-Counter 7-1 Chapter 7 Time Base Counter ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 7 Time Base Counter HSCLK (500kHz/2MHz) RESET (Internal signal) Data bus Figure 7-2 Configuration of High-Speed Time Base Counter Note: The frequency of HSCLK changes according to specified data in OSCM2, SYSC1, and SYSC0 bits of Frequency control register 0 (FON0). HTBDR 1/n-Counter R 8 HTBDR : High-speed time base counter frequency divide register ...
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... High-speed time base counter 0F00BH frequency divide register Low-speed time base counter 0F00CH frequency adjustment register L Low-speed time base counter 0F00DH frequency adjustment register H ML610Q407/ML610Q408/ML610Q409 User's Manual Name Symbol (Byte) LTBR HTBDR LTBADJL LTBADJH 7-3 Chapter 7 Time Base Counter Symbol (Word) ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 7 Time Base Counter 7.2.2 Low-Speed Time Base Counter Register (LTBR) Address: 0F00AH Access: R/W Access size: 8-bit Initial value: 00H 7 LTBR T1HZ R/W R/W Initial value 0 LTBR is a special function register (SFR) to read the T128HZ to T1HZ outputs of the low-speed time base counter. ...
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... The HTD3-HTD0 bits are used to set the dividing ratio of the 4-bit, 1/n counter. The frequency divide ratios selectable include 1/1 to 1/16. HTD3 HTD2 *1: Indicates the frequency when the high-speed oscillation clock, HSCLK, is 500 kHz. ML610Q407/ML610Q408/ML610Q409 User's Manual − − HTD3 R/W R/W R HTD1 HTD0 Dividing ratio 0 0 1/16 (initial value 1/10 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 7 Time Base Counter 7.2.4 Low-Speed Time Base Counter Frequency Adjustment Registers L and H (LTBADJL, LTBADJH) Address: 0F00CH Access: R/W Access size: 8/16 bit Initial value: 00H 7 LTBADJL LADJ7 R/W R/W Initial value 0 Address: 0F00DH Access: R/W Access size: 8-bit ...
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... T128HZ T64HZ T32HZ T16HZ T16HZ T8HZ T4HZ T2HZ T1HZ Figure 7-4 Interrupt Timing and Reset Timing by Writing to LTBR ML610Q407/ML610Q408/ML610Q409 User's Manual ; EA LTBR address [EA] ; 1st read [EA] ; 2nd read R1 ; Comparison for LTBR ; To MARK when the values do not coincide 7-7 Chapter 7 Time Base Counter ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 7 Time Base Counter 7.3.2 High-Speed Time Base Counter The high-speed time base counter is configured as a 4-bit 1/n counter ( 16). In the 4-bit 1/n counter, the divided clock (1/16 x HSCLK to 1/1 x HSCLK) selected by the high-speed time base counter divide register (HTBDR) is generated as HTBCLK. HTBCLK is used as a timer and also as an operation clock of PWM ...
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... The low-speed clock (LSCLK) and the outputs of T32KHZ and T16KHZ of LTBC are not adjusted by the frequency adjust function. The frequency adjustment accuracy does not guarantee the accuracy including the frequency variation of the crystal oscillation (32.768kHz) due to temperature variations. ML610Q407/ML610Q408/ML610Q409 User's Manual LADJ10∼ ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 7 Time Base Counter 7.3.4 A signal generation for 16-bit timer 2-3 frequency measurement mode A signal (437C) used for 16-bit timer 0-1 frequency measurement mode is generated from the output clock of the low-speed time base counter. See Chapter 9, “Timer” for more detail about the frequency measurement mode. ...
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Chapter 8 Capture ...
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... Pin name I/O Capture 0 input pin P00/CAP0 I Used as the secondary function of the P00 pin. Capture 1 input pin P01/CAP1 I Used as the secondary function of the P01 pin. ML610Q407/ML610Q408/ML610Q409 User's Manual Capture Contoroller CAPSTAT CAPCON CP1F CP0F R R Figure 8-1 Configuration of Capture Circuit Function ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 8 Capture 8.2 Description of Registers 8.2.1 List of Registers Address 0F090H Capture control register 0F091H Capture status register 0F092H Capture data register 0 0F093H Capture data register 1 0F094H Capture time base data register Name Symbol (Byte) CAPCON CAPSTAT CAPR0 CAPR1 ...
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... Stops the capture 0 operation. (initial value) 1 Starts the capture 0 operation. • ECAP1 (bit 1) The ECAP1 bit is used to start or stop the operation of capture 1. ECAP1 0 Stops the capture 1 operation. (initial value) 1 Starts the capture 1 operation. ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W R/W 0 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 8 Capture 8.2.3 Capture Status Register (CAPSTAT) Address: 0F091H Access: R Access size: 8-bit Initial value: 00H 7 CAPSTAT — R/W R Initial value 0 CAPSTAT is a read-only, special function register (SFR) to indicate a state of the capture circuit. [Description of Bits] • CAPF0 (bit 0) The CAPF0 bit is the flag to indicate whether data is captured in capture data register 0 (CARP0) or not. When the CAPF0 bit is set to " ...
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... The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P00 interrupt request is generated with the CAPF0 flag (bit 0 of the CAPSTAT register) set to "0". Writing to CAPR0 sets the CAPF0 flag of CAPSTAT to "0". The value of CAPR0 does not change even if data is written to it. ML610Q407/ML610Q408/ML610Q409 User's Manual ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 8 Capture 8.2.5 Capture Data Register 1 (CAPR1) Address: 0F093H Access: R/W Access size: 8-bit Initial value: 00H 7 CAPR1 CP17 R/W R/W Initial value 0 CAPR1 is a register in which capture data is stored. The T4KHZ to T32HZ signals of the low-speed time base counter (LTBC) are captured when the P01 interrupt request is generated with the CAPF1 flag (bit 1 of the CAPSTAT register) set to " ...
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... The initial value varies depending on the state of the T4KHZ to T32HZ outputs of the low-speed time base counter (LTBC) at the timing when this register is read. When reading the data, read this register twice and check that the two values coincide to prevent reading of undefined data during counting. ML610Q407/ML610Q408/ML610Q409 User's Manual 6 5 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 8 Capture 8.3 Description of Operation The capture circuit starts the capture operation by setting the ECAP0 or ECAP1 bit of the capture control register (CAPCON). When the input trigger from the P00 or P01 pin selected by the external interrupt control register (EXICON0 or EXICON1) is generated and the P00 or P01 interrupt request flag (QP00 or QP01) is set to “ ...
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Chapter 9 Timer ...
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... Write TMnC LSCLK HTBCLK External clock P04/T02P0CK P44/T02P0CK Data bus P45/T13CK Write TMnC Write TMmC LSCLK HTBCLK External clock P04/T02P0CK P44/T02P0CK Read TMnC Data bus ML610Q407/ML610Q408/ML610Q409 User's Manual Comparator 8 TMnCON0 TnCK R TMnC TMnCON1 8 (a) In 8-bit Timer Mode (Timers TMnCON0 TnCK R TMnC TMnCON1 8 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer Low-speed time base counter (LTBC) Counter External clock P04/T02P0CK P44/T02P0CK (c) Frequency measurement mode with 16 bit timer(Timer2 to 3) 9.1.3 List of Pins Pin name I/O External clock input pin P04/T02P0CK I 8bit timer mode : used for timer0 or timer2 16bit timer mode : used for timer0 to timer1 or timer2 to timer3. ...
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... Timer 2 control register 0 0F03BH Timer 2 control register 1 0F03CH Timer 3 data register 0F03DH Timer 3 counter register 0F03EH Timer 3 control register 0 0F03FH Timer 3 control register 1 ML610Q407/ML610Q408/ML610Q409 User's Manual Symbol (Byte) Symbol (Word) TM0D TM0DC TM0C TM0CON0 TM0CON TM0CON1 TM1D TM1DC TM1C TM1CON0 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.2 Timer 0 Data Register (TM0D) Address: 0F030H Access: R/W Access size: 8-bit Initial value: 0FFH 7 TM0D T0D7 R/W R/W Initial value 1 TM0D is a special function register (SFR) to set the value to be compared with the timer 0 counter register (TM0C) value ...
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... TM1D is a special function register (SFR) to set the value to be compared with the value of the timer 1 counter register (TM1C). Note: Set TM1D when the timer stops(When T1STAT bit of TM1CON1 register is “0”). When “00H” is written in TM1D, TM1D is set to “01H”. ML610Q407/ML610Q408/ML610Q409 User's Manual T1D5 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.4 Timer 2 Data Register (TM2D) Address: 0F038H Access: R/W Access size: 8-bit Initial value: 0FFH 7 TM2D T2D7 R/W R/W Initial value 1 TM2D is a special function register (SFR) to set the value to be compared with the value of the timer 2 counter register (TM2C) ...
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... TM3D is a special function register (SFR) to set the value to be compared with the value of the timer 3 counter register (TM3C). Note: Set TM3D when the timer stops(When T3STAT bit of TM3CON1 register is “0”). When “00H” is written in TM3D, TM3D is set to “01H”. ML610Q407/ML610Q408/ML610Q409 User's Manual T3D5 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.6 Timer 0 Counter Register (TM0C) Address: 0F031H Access: R/W Access size: 8-bit Initial value: 00H 7 TM0C T0C7 R/W R/W Initial value 0 TM0C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM0C is performed, TM0C is set to “00H”. The data that is written is meaningless. ...
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... Table 9-2 TM1C Read Enable/Disable during Timer Operation Timer clock System clock T1CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q407/ML610Q408/ML610Q409 User's Manual T1C5 T1C4 T1C3 R/W R/W R TM1C read enable/disable Read enabled. Read enabled. However, to prevent the reading of undefined data during incremental counting, read TM1C twice and check that the results match ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.8 Timer 2 Counter Register (TM2C) Address: 0F039H Access: R/W Access size: 8-bit Initial value: 00H 7 TM2C T2C7 R/W R/W Initial value 0 TM2C is a special function register (SFR) that functions as an 8-bit binary counter. When write operation to TM2C is performed, TM2C is set to “00H”. The data that is written is meaningless. ...
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... Table 9-4 TM3C Read Enable/Disable during Timer Operation Timer clock System clock T3CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q407/ML610Q408/ML610Q409 User's Manual T3C5 T3C4 T3C3 R/W R/W R TM3C read enable/disable Read enabled. Read enabled. However, to prevent the reading of undefined data during incremental counting, read TM3C twice and check that the results match ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.10 Timer 0 Control Register 0 (TM0CON0) Address: 0F032H Access: R/W Access size: 8-bit Initial value: 00H 7 TM0CON0 — R/W R/W Initial value 0 TM0CON0 is a special function register (SFR) to control the Timer 0. Rewrite TM0CON0 while the timer 0 is stopped (T0STAT of the TM0CON1 register is “0”). ...
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... The T1CS1 and T1CS0 bits are used for selecting the operation clock of timer 1. LSCLK, HTBCLK, or the external clock (P45/T13CK) can be selected by these bits. In cases where the 16-bit timer mode has been selected by setting T01M16 of TM0CON to “1”, the values of T1CS1 and T1CS0 are invalid. T1CS1 T1CS0 ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W R/W R Description ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.12 Timer 2 Control Register 0 (TM2CON0) Address: 0F03AH Access: R/W Access size: 8-bit Initial value: A0H 7 TM2CON0 T2FMA7 R/W R Initial value 1 TM2CON0 is a special function register (SFR) to control the Timer 2. Rewrite TM2CON0 while the timer 2 is stopped (T2STAT of the TM2CON1 register is “0”). ...
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... The T3CS1 and T3CS0 bits are used for selecting the operation clock of timer 3. LSCLK, HTBCLK, or the external clock (P44/T13CK) can be selected by these bits. In cases where the 16-bit timer mode has been selected by setting T23M16 of TM2CON to “1”, the values of T3CS1 and T3CS0 are invalid. T3CS1 T3CS0 ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W R/W R Description ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.14 Timer 0 Control Register 1 (TM0CON1) Address: 0F033 Access: R/W Access size: 8-bit Initial value: 00H 7 TM0CON1 T0STAT R/W R Initial value 0 TM0CON1 is a special function register (SFR) to control the Timer 0. [Description of Bits] • T0RUN (bit 0) The T0RUN bit is used for controlling stop/start of timer 0. ...
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... Starts counting. • T1STAT (bit 7) The T1STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 1. In 16-bit timer mode, this bit will read “0”. T1STAT 0 Counting stopped. 1 Counting in progress. ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W R/W 0 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.2.16 Timer 2 Control Register 1 (TM2CON1) Address: 0F03BH Access: R/W Access size: 8-bit Initial value: 00H 7 TM2CON1 T2STAT R/W R Initial value 0 TM2CON1 is a special function register (SFR) to control the Timer 2. [Description of Bits] • T2RUN (bit 0) The T2RUN bit is used for controlling stop/start of timer 2. ...
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... The T3STAT bit is used for indicating “counting stopped”/”counting in progress” of timer 3. In 16-bit timer mode and 16-bit timer frequency measurement mode, this bit will return “0”. T3STAT 0 Counting stopped. 1 Counting in progress. ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.3 Description of Operation 9.3.1 Timer mode operation The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer clocks (TnCK) that are selected by the Timer control register 0 (TMnCON0) when the TnRUN bits of timer control register 1 (TMnCON1) are set to “ ...
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... TM2CON0 register) to “1” (16bit mode) and set T2CS1-0 bits(bit1/0 of TM2CON0 register) to “01”(HTBCLK mode). (4) Set “FFH” to both TM2D register and TM3D register. (5) Clear both TM2C register and TM3C register to “00H”. (6) Set T2RUN bit (bit0 of TM2CON1 register) to “1” to start counting the timer. ML610Q407/ML610Q408/ML610Q409 User's Manual (8) (7) (6) ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer (7) When (T23MFM bit == "1") and (TM23M16 bit == "1") and (T2RUN bit == "1"), the count up starts with the falling of the 64Hz clock signal. (8) The count-up stops at the falling edge of the next timer clock (HTBCLK) after 437C signal becomes “1”. ...
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... Round off {N1/32 (5bit right-shift (minus) 1. 4800 Round off {N1/64 (6bit right-shift (minus) 1. 9600 Round off {N1/128 (7bit right-shift (minus) 1. 19200 Round off {N1/256 (8bit right-shift (minus) 1. 38400 Round off {N1/512 (9bit right-shift (minus) 1. ML610Q407/ML610Q408/ML610Q409 User's Manual 9-23 Chapter 9 Timer Theoretical accuracy ~ ±2% ±2% ~ 2.5% ±2.5% ~ ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer Table 9-6 Baud Rate and Accuracy (theoretical) for Baud Rate Clock Set to 2MHz Baud-rate[bps] Data setting to UA0BRTH register and UA0BRTH register 300 Round off {N1/4 (2bit right-shift (minus) 1. 600 Round off {N1/8 (3bit right-shift (minus) 1. 1200 Round off {N1/16 (4bit right-shift (minus) 1 ...
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... Register name Bit 7 P47DIR Bit name Setting * value Select the external clock(P44/T02P0CK) and timer0 (8-bit mode) in the TM0CON0 register, and input the operation clock for the Timer 0 from the P44 pin. ML610Q407/ML610Q408/ML610Q409 User's Manual P4MOD1 register (Address: 0F225H P46MD1 P45MD1 P44MD1 * * 0 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.4.3 Operating Timer 1 (8-Bit Timer Mode) by External Clock (P45/T13CK) Set the P45MD1 bit (P4MOD1 register's bit 5) to "0" and the P45MD0 bit (P4MOD0 register's bit 5) to "0" for specifying the P45 to the 1st function. Register name ...
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... Bit 7 P47DIR P46DIR Bit name Setting * value Select the external clock(P44/T02P0CK) and timer2 (8-bit mode) in the TM2CON0 register, and input the operation clock for the Timer 2 from the P44 pin. ML610Q407/ML610Q408/ML610Q409 User's Manual P4MOD1 register (Address: 0F225H P45MD1 P44MD1 P43MD1 * * 0 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.4.6 Operating Timer 3 (8-Bit Timer Mode) by External Clock (P45/T13CK) Set the P45MD1 bit (P4MOD1 register's bit 5) to "0" and the P45MD0 bit (P4MOD0 register's bit 5) to "0" for specifying the P45 to the 1st function. Register name ...
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... P46DIR Bit name Setting * value Select the external clock(P44/T02P0CK) and Timers 0 and 1 (16-bit mode) in the TM0CON0 register, and input the operation clock for the Timers 0 and 1 (16-bit mode) from the P44 pin. ML610Q407/ML610Q408/ML610Q409 User's Manual P4MOD1 register (Address: 0F225H P45MD1 P44MD1 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 9 Timer 9.4.9 Operating Timer 2 and Timer 3 (16-Bit Timer Mode) by External Clock (P44/T02P0CK) Set the P44MD1 bit (P4MOD1 register's bit 4) to "0" and the P44MD0 bit (P4MOD0 register's bit 4) to "0" for specifying the P44 to the 1st function. ...
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Chapter 10 PWM ...
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... PW0PBUF : PWM0 period buffer PW0DL : PWM0 duty register L PW0DH : PWM0 duty register H PW0DBUF : PWM0 duty buffer PW0CL : PWM0 counter register L PW0CH : PWM0 counter register H PW0CON0 : PWM0 control register 0 PW0CON1 : PWM0 control register 1 ML610Q407/ML610Q408/ML610Q409 User's Manual P0NEG P0FLG 16 R PW0CON0 P0CK PW0CH/L PW0CON1 PW0CH latch 8 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 10 PWM 10.1.3 List of Pins Pin name Input/output PWM0 external clock input pin P04/T02P0CK I Used for the primary function of the P04 pin. PWM0 external clock input pin P44/T02P0CK I Used for the primary function of the P44 pin. PWM0 output pin ...
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... P0P14 R/W R/W R/W Initial value 1 PW0PH and PW0PL are special function registers (SFRs) to set the PWM0 periods. Note: When PW0PH or PW0PL is set to “0000H”, the PWM0 period buffer (PW0PBUF) is set to “0001H”. ML610Q407/ML610Q408/ML610Q409 User's Manual P0P5 P0P4 P0P3 R/W R/W ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 10 PWM 10.2.3 PWM0 Duty Registers (PW0DL, PW0DH) 7 PW0DL P0D7 R/W R/W Initial value 0 Address: 0F0A2H Access: R/W Access size: 8-bit Initial value: 00H 7 PW0DH P0D15 R/W R/W Initial value 0 Address: 0F0A3H Access: R/W Access size: 8-bit Initial value: 00H PW0DH and PW0DL are special function registers (SFRs) to set the duties of PWM0 ...
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... Table 10-1 shows PW0CH and PW0CL read enable/disable for each combination of the PWM clock and system clock. Table 10-1 PW0CH and PW0CL Read Enable/Disable during PWM0 Operation PWM clock System clock P0CK SYSCLK LSCLK LSCLK LSCLK HSCLK HTBCLK LSCLK HTBCLK HSCLK LSCLK External clock HSCLK ML610Q407/ML610Q408/ML610Q409 User's Manual P0C5 P0C4 P0C3 R/W R/W R P0C13 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 10 PWM 10.2.5 PWM0 Control Register 0 (PW0CON0) 7 PW0CON0 — R/W R/W Initial value 0 Address: 0F0A6H Access: R/W Access size: 8-bit Initial value: 00H PW0CON0 is a special function register (SFR) to control PWM. [Description of Bits] • P0CS1, P0CS0 (bits 1, 0) The P0CS1 and P0CS0 bits are used to select the PWM0 operation clocks ...
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... P0FLG 0 PWM0 output flag = “0” 1 PWM0 output flag = “1” (initial value) • P0STAT (bit 7) The P0STAT bit indicates “counting stopped or “counting in progress” of PWM0. P0STAT 0 Counting stopped. (Initial value) 1 Counting in progress. ML610Q407/ML610Q408/ML610Q409 User's Manual — — R/W R/W R Description ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 10 PWM 10.3 Description of Operation The PWM0 counter registers (PW0CH, PW0CL) are set to an operating state (P0STAT is set to “1”) on the first falling edge of the PWM clock (P0CK) that are selected by the PWM0 control register 0 (PW0CON0) when the P0RUN bit of PWM0 control register 1 (PW0CON1) is set to “ ...
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... Even if “0” is written to the P0RUN bit, counting operation continues up to the falling edge (the PWM0 status flag (P0STAT “1” state) of the next PWM clock pulse. Therefore, the PWM0 interrupt (PW0INT) may occur. ML610Q407/ML610Q408/ML610Q409 User's Manual 0001 0002 7FFF 8000 8001 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 10 PWM 10.4 Specifying port registers To output the PWM waveform, the applicable bit of each related port register needs to be set. See Chapter 17, “Port 4” and Chapter 15, “Port 2” for detail about the port registers. 10.4.1 Functioning the P43 pin (PWM0) as the PWM output Set P43MD1 bit (bit3 of P4MOD1 register) to “ ...
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... The P24D bit (P2D register bit 4) data can either be "0" or "1". Register name Bit 7 - Bit name Setting value - - : Bit that does not exist * : Bit not related to the PWM function ** : Don’t care ML610Q407/ML610Q408/ML610Q409 User's Manual P2MOD register (Address: 0F214H P24MD - - - ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 10 PWM 10.4.3 Operating PWM0 with External Clock (P04/T02P0CK) Set the P04E0 bit (EXICON0 register's bit 4) to "0" and the P04E1 bit (EXICON1 register's bit 4) to "0" for specifying the P04 external interrupt to Disable. Register name Bit 7 - Bit name ...
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... Set the P0CS1 bit (PW0CON0 register's bit 1) to "1" and the P0CS0 bit (PW0CON0 register's bit 0) to "1". Register name Bit 7 — Bit name Setting value * Input the operation clock for the PWM0 from the P44 pin. ML610Q407/ML610Q408/ML610Q409 User's Manual P4MOD1 register (Address: 0F225H P46MD1 P45MD1 P44MD1 P43MD1 ...
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Chapter 11 Watchdog Timer ...
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Watchdog Timer 11.1 Overview This LSI incorporates a watchdog timer (WDT) that operates at a system reset unconditionally (free-run operation) in order to detect an undefined state of the MCU and return from that state. If the WDT counter ...
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Chapter 11 Watchdog Timer 11.2 Description of Registers 11.2.1 List of Registers Address 0F00EH Watchdog timer control register 0F00FH Watchdog timer mode register Name Symbol (Byte) WDTCON WDTMOD 11-2 Symbol (Word) R/W Size Initial value — R/W 8 — R/W ...
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... WDT when the first overflow WDT interrupt occurs and also the codes run at high-speed system clock, please check the WDP gets reversed after writing to WDTCON to see if the writing was surely successful. For example of the program code, see Section 11.3.1, "Handling example when you do not want to use the watch dog timer". ML610Q407/ML610Q408/ML610Q409 User's Manual ...
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Chapter 11 Watchdog Timer 11.2.3 Watchdog Timer Mode Register (WDTMOD) Address: 0F00FH Access: W Access size: 8-bit Initial value: 02H 7 WDTMOD — R/W R/W Initial value 0 WDTMOD is a special function register to set the overflow period of ...
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... WOV mode register (WDTMOD). Clear the WDT counter within the clear period of the WDT counter (T WDT1 WDT0 ML610Q407/ML610Q408/ML610Q409 User's Manual ) of the WDT counter, one of 125ms, 500ms, 2s, and 8s can be selected by the watchdog Table 11-1 Clear Period of WDT Counter T WOV 0 125ms 500ms 1 2000ms ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 11 Watchdog Timer Figure 11-2 shows an example of watchdog timer operation. Low-Speed Clock Oscillation RESET_S System reset Data: WDTCON Write WDTP Internal pointer WDT counter WDTINT WDT interrupt WDT reset Figure 11-2 Example of Watchdog Timer Operation ① The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start. ② ...
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... Therefore needed to clear the WDT counter even if you do not want to use the WDT as a fale-safe function. See following example programming codes to clear the WDT counter in the interrupt routine. Example programming code: __DI(); do { WDTCON = 0x5a; } while(WDP != 1) WDTCON = 0xa5; __EI(); ML610Q407/ML610Q408/ML610Q409 User's Manual // Disable multi-interrupts 11-7 Chapter 11 Watchdog Timer ...
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Synchronous Serial Port Chapter 12 ...
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Synchronous Serial Port 12.1 Overview This LSI includes two channels of 8/16-bit synchronous serial ports (SSIO). It can also be used to control the device incorporated with the SPI interface by using one GPIO as the chip enable pin. ...
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Chapter 12 Synchronous Serial Port SIO0BUFL, SIO1BUFL SIO0BUFH, SIO1BUFH SIO0CON, SIO1CON SIO0MOD0, SIO1MOD0 SIO0MOD1, SIO1MOD1 Figure 12-1 Configuration of Synchronous Serial Port 12.1.3 List of Pins Pin name I/O P40/SIN0 I P44/SIN0 P41/SCK0 I/O P45/SCK0 P42/SOUT0 O P46/SOUT0 P50/SIN1 I ...
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... SIO0BUFL and SIO0BUFH are special function registers (SFRs) to write transmitted data and to read received data of the synchronous serial port 0. When data is written in SIO0BUFL and SIO0BUFH, the data is written in the transmit registers (SIO0TRL and SIO0TRH). When data is read from SIO0BUFL and SIO0BUFH, the contents of the receive registers (SIO0RCL and SIO0RCH) are read. ML610Q407/ML610Q408/ML610Q409 User's Manual S0B5 ...
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Chapter 12 Synchronous Serial Port 12.2.3 Serial Port 1 Transmit/Receive Buffers (SIO1BUFL and SIO1BUFH) Address: 0F288H Access: R/W Access size: 8 bits/16 bits Initial value: 00H 7 S1B7 SIO1BUFL R/W R/W Initial value 0 Address: 0F289H Access: R/W Access size: ...
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... The S1EN bit is used to specify start of synchronous serial communication. Writing a “1” to S1EN starts 8-/16-bit data communication. The S1EN bit is set to “0” automatically when 8-/16-bit data communication is terminated. The S1EN bit is set to “0” system reset. S1EN 0 Stops communication. (Initial value) 1 Starts communication ML610Q407/ML610Q408/ML610Q409 User's Manual — — — R/W R/W ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 12 Synchronous Serial Port 12.2.6 Serial Port 0 Mode Register 0 (SIO0MOD0) Address: 0F284H Access: R/W Access size: 8-bit Initial value: 00H 7 SIO0MOD0 — R/W R/W Initial value 0 SIO0MOD0 is a special function register (SFR) to set mode of the synchronous serial port 0. ...
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... Note: •Do not change any of the SIO1MOD0 register settings during transmission/reception. •When the synchronous serial port 1 is used, the tertiary functions of Port 5 must be set. For the tertiary functions of Port 5, see Chapter 18, “Port 5”. ML610Q407/ML610Q408/ML610Q409 User's Manual — — — ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 12 Synchronous Serial Port 12.2.8 Serial Port 0 Mode Register 1 (SIO0MOD1) Address: 0F285H Access: R/W Access size: 8-bit Initial value: 00H 7 SIO0MOD1 — R/W R/W Initial value 0 SIO0MOD1 is a special function register (SFR) to set mode of the synchronous serial port 0. ...
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... Clock type 0: Output at the “H” level by default (initial value). 1 Clock type 1: Output at the “L” level by default. • S1NEG (bit 5) The S1NEG bit is used to select the positive or negative logic of the transfer clock output. S1NEG 0 Positive logic (initial value) 1 Negative logic ML610Q407/ML610Q408/ML610Q409 User's Manual — S1NEG S1CKT R/W R ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 12 Synchronous Serial Port 12.3 Description of Operation 12.3.1 Transmit Operation When “1” is written to the SnMD1 bit and "0" is written to the SnMD0 bit of the serial port mode register (SIOnMOD0), this LSI is set to the transmit mode. When transmitted data is written to the serial port transmit/receive buffer (SIOnBUFL, "H") and the SnEN bit of the serial port control register (SIOnCON) is set to “ ...
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SnEN SCKn SIOnTRH,L SOUTn SIOnINT Figure 12-5 Transmit Operation Waveforms of Synchronous Serial Port for Clock Type 1 (Negative Logic) Transmitted data (8-bit length, LSB first 12-11 Chapter 12 Synchronous Serial ...
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Chapter 12 Synchronous Serial Port 12.3.2 Receive Operation When “0” is written to the SnMD1 bit and “1” is written to the SnMD0 bit of the serial port mode register (SIOnMOD0), this LSI is set to a receive mode. When ...
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... When the SOUT0 pin is set to the tertiary function output in receive mode, a “H” level is output from the SOUT0 pin. When the SOUT1 pin is set to the tertiary function output in receive mode, a “H” level is output from the SOUT1 pin. ML610Q407/ML610Q408/ML610Q409 User's Manual ...
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Chapter 12 Synchronous Serial Port 12.3.3 Transmit/Receive Operation When “1” is written to the SnMD1 bit and "1" is written to the SnMD0 bit of the serial port mode register (SIOnMOD0), this LSI is set to the transmit/receive mode. When ...
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... The data of the P42D to P40D bits (P4D register bits can either be "0" or "1". Register name Bit 7 P47D Bit name Setting value * * : Bit not related to the SSIO0 function ** : Don’t care ML610Q407/ML610Q408/ML610Q409 User's Manual P4MOD1 register (Address: 0F225H P46MD1 P45MD1 P44MD1 P43MD1 * ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 12 Synchronous Serial Port 12.4.2 Functioning P42 (SOUT0: Output), P41 (SCK0: Input/output), and P40 (SIN0: Input) as the SSIO0/ ”Slave mode” Set the P42MD1 to P40MD1 bits (P4MOD1 register bits “1” and the P42MD0 to P40MD0 bits (P4MOD0 register bits “0” for selecting the SSIO as the tertiary function of the P42, P41 and P40. They are the same setting as those in the case of master mode ...
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... The P46D to P44D bits (P4D register bits data can either be "0" or "1" (not need to be set). Register name Bit 7 P47D Bit name Setting value * * : Bit not related to the SSIO0 function ** : Don’t care ML610Q407/ML610Q408/ML610Q409 User's Manual P4MOD1 register (Address: 0F225H P46MD1 P45MD1 P44MD1 P43MD1 1 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 12 Synchronous Serial Port 12.4.4 Functioning P46 (SOUT0: Output), P45 (SCK0: Input/output) and P44 (SIN0: Input) as the SSIO0/ ”Slave mode” Set P46MD1-P44MD1 bits(bit6-bit4 of P4MOD1 register) to “1” and set P46MD0-P44MD0(bit6-bit4 of P4MOD0 register) to “0”, for specifying the SSIO0 as the tertialy function of P46, P45 and P44. Set P40MD1 bit(bit0 of P4MOD1) to “ ...
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... The P52D to P50D bits (P5D register bits data can either be "0" or "1" (not need to be set). Register name Bit 7 P57D Bit name Setting value * * : Bit not related to the SSIO1 function ** : Don’t care ML610Q407/ML610Q408/ML610Q409 User's Manual P5MOD1 register (address: 0F22DH P56MD1 P55MD1 P54MD1 * * ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 12 Synchronous Serial Port 12.4.6 Functioning P52 (SOUT1: Output), P51 (SCK1: Input/output), and P50 (SIN1: Input) as the SSIO1/ ”Slave mode” Set the P52MD1 to P50MD1 bits (P5MOD1 register bits "1", and set the P52MD0 to P50MD0 bits (P5MOD0 register bits "0" for specifying the SSIO as the tertialy function of the P52, P51, and P50. They are the same setting as those in the case of master mode ...
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Functioning P56 (SOUT1: Output), P55 (SCK1: Input/output), and P54 (SIN1: Input) as the SSIO1/ “Master mode” Set the P56MD1 to P54MD1 bits (P5MOD1 register bits "1", and set the P56MD0 to P54MD0 bits (P5MOD0 register ...
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Chapter 12 Synchronous Serial Port 12.4.8 Functioning P56 (SOUT1: Output), P55 (SCK1: Input/output), and P54 (SIN1: Input) as the SSIO1/ ”Slave mode” Set the P56MD1 to P54MD1 bits (P5MOD1 register bits "1", and set the P56MD0 ...
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Chapter 13 UART ...
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... Data bus UA0BUF : UART0 transmit/receive buffer UA0BRTH,L : UART0 baud rate H and L are: UA0CON : UART0 control register UA0MOD0,1 : UART0 mode registers 0 and 1 UA0STAT : UART0 status register ML610Q407/ML610Q408/ML610Q409 User's Manual Shift Register UART Band Rate Controller Generator UA0CON UA0BRTH,L UA0BUF UA0MOD0,1 Figure 13-1 Configuration of UART ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 13 UART 13.1.3 List of Pins Pin name I/O UART0 data input pin P02/RXD0 I Used for the primary function of the P02 pin. UART0 data input pin P42/RXD0 I Used for the secondary function of the P42 pin. UART0 data output pin ...
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... The bits, which are not required when any of the 5- to 8-bit data length is selected, become invalid in transmit mode and are set to “0” in receive mode. Note: For operation in transmit mode, be sure to set the transmit mode (UA0MOD0 and UA0MOD1) before setting the transmitted data in UAOBUF. ML610Q407/ML610Q408/ML610Q409 User's Manual U0B5 ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 13 UART 13.2.3 UART0 Control Register (UA0CON) Address: 0F291H Access: R/W Access size: 8-bit Initial value: 00H 7 ― UA0CON R/W R/W Initial value 0 UA0CON is a special function register (SFR) to start/stop communication of the UART. [Description of Bits] • U0EN (bit 0) The U0EN bit is used to specify the UART communication operation start. When U0EN is set to “ ...
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... LSCLK X 2 for the clock, enable the operation of the low-speed double clock by setting bit 2 (ENMLT) of the frequency control register 1 (FCON1) to “1”. •When selecting the P42 pin as the received data input pin necessary to configure settings for the Port 4 secondary functions. For the secondary functions of Port 4, see Chapter 17, “Port 4”. ML610Q407/ML610Q408/ML610Q409 User's Manual － ...
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... ML610Q407/ML610Q408/ML610Q409 User's Manual Chapter 13 UART 13.2.5 UART0 Mode Register 1 (UA0MOD1) Address: 0F293H Access: R/W Access size: 8/16 bit Initial value: 00H 7 － UA0MOD1 R/W R/W Initial value 0 UA0MOD1 is a special function register (SFR) to set the transfer mode of the UART. [Description of Bits] • ...