ICS9FGP202AKLF IDT, Integrated Device Technology Inc, ICS9FGP202AKLF Datasheet - Page 12

• Manufacturer Part Number: ICS9FGP202AKLF
• Description: IC FREQ TIMING GENERATOR 40VFQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr
• Series: -r

Specifications of ICS9FGP202AKLF

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 400MHz
• Number Of Elements: 3
• Supply Current: 200mA
• Pll Input Freq (min): 25MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: VFQFPN EP
• Output Frequency Range: 25 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9FGP202AKLF

1339C—09/14/09
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address *D0
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 1.
Byte N + X -1
(see Note 2)
WR
P
T
Beginning Byte N
Slave Address *D0
Data Byte Count = X
Index Block Write Operation
General SMBus serial interface information for the ICS9FGP202A
Beginning Byte = N
Byte N + X - 1
Controller (Host)
Integrated
Circuit
Systems, Inc.
starT bit
stoP bit
WRite
(H)
ICS (Slave/Receiver)
ACK
ACK
ACK
ACK
ACK
(H)
12
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address *D0
• ICS clock will acknowledge
• Controller (host) sends the begining byte
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address *D1
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
location = N
was written to byte 8)
WR
RD
RT
N
P
T
Slave Address *D0
Slave Address *D1
Index Block Read Operation
Beginning Byte = N
Controller (Host)
Not acknowledge
ACK
ACK
Repeat starT
starT bit
stoP bit
WRite
ReaD
(H)
(H)
.
ICS (Slave/Receiver)
Data Byte Count = X
ICS9FGP202A
Beginning Byte N
Byte N + X - 1
ACK
ACK
ACK
(H)
(H)
(H)