ICS9FGP202AKLF IDT, Integrated Device Technology Inc, ICS9FGP202AKLF Datasheet - Page 7

• Manufacturer Part Number: ICS9FGP202AKLF
• Description: IC FREQ TIMING GENERATOR 40VFQFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr
• Series: -r

Specifications of ICS9FGP202AKLF

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 400MHz
• Number Of Elements: 3
• Supply Current: 200mA
• Pll Input Freq (min): 25MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: VFQFPN EP
• Output Frequency Range: 25 to 400MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 9FGP202AKLF

1339C—09/14/09
1
1
2
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Output Parameters
Maximum difference across all
Guaranteed by design and characterization, not 100% tested in production.
Guaranteed by design and characterization, not 100% tested in production.
Input frequency should be measured at the REF pin and tuned to ideal 25.00MHz to meet ppm frequency accuracy on PLL outputs.
Input ESD protection HBM
Ambient Operating Temp
Low-level Output Voltage
Junction Temperature
Modulation Frequency
Clock/Data Rise Time
Storage Temperature
Low Threshold Input-
Low Threshold Input-
Clock/Data Fall Time
3.3V Supply Voltage
Powerdown Current
Input High Current
Input High Voltage
Input Low Current
Operating Current
Input Capacitance
Input Low Voltage
Current sinking at
Input Frequency
Clk Stabilization
Pin Inductance
SMBus Voltage
PARAMETER
PARAMETER
SCLK/SDATA
SCLK/SDATA
High Voltage
Low Voltage
Integrated
Circuit
Systems, Inc.
Tdrive_PD
V
Trise_PD
VDD pins
Tfall_PD
OL
= 0.4 V
SYMBOL
SYMBOL
VDDdelta
Tambient
ESD prot
VDDxxx
I
I
I
V
DD3.3OP
DD3.3PD
V
T
PULLUP
C
T
T
C
L
C
V
V
V
V
I
I
IH_FS
IL_FS
STAB
Ts
I
F
IL1
IL2
RI2C
FI2C
Tj
OUT
IH
pin
INX
DD
OL
IH
IL
IN
i
V
IN
V
all differential pairs tri-stated
From VDD Power-Up or de-
assertion of PD to 1st clock
IN
= 0 V; Inputs with no pull-up
CPU output enable after
Output pin capacitance
Triangular Modulation
= 0 V; Inputs with pull-up
(Max VIL - 0.15) to
(Min VIH + 0.15) to
all diff pairs driven
all outputs driven
(Min VIH + 0.15)
(Max VIL - 0.15)
PD de-assertion
CONDITIONS*
PD rise time of
PD fall time of
CONDITIONS
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
V
resistors
@ I
resistors
DD
IN
= 3.3 V
= V
PULLUP
-
-
-
-
-
-
DD
7
GND - 0.5
V
V
SS
SS
-200
MIN
2000
0.7
2.7
MIN
30
-5
-5
-65
2
4
- 0.3
- 0.3
0
25.00000
TYP
3.3V
TYP
V
V
GND + 4.5
DD
DD
MAX
1000
0.35
200
300
300
0.8
2.5
MAX
5.5
0.4
30
33
150
125
0.5
+ 0.3
5
+ 0.3
8
7
4
5
5
5
5
70
ICS9FGP202A
UNITS
UNITS
MHz
kHz
mA
mA
mA
nH
ms
mA
uA
uA
uA
pF
pF
pF
us
ns
ns
ns
ns
V
V
V
V
V
V
°C
°C
°
V
V
V
C
Notes
Notes
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1