ICS9FGP202AKLF IDT, Integrated Device Technology Inc, ICS9FGP202AKLF Datasheet - Page 13

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ICS9FGP202AKLF

Manufacturer Part Number
ICS9FGP202AKLF
Description
IC FREQ TIMING GENERATOR 40VFQFN
Manufacturer
IDT, Integrated Device Technology Inc
Type
Frequency Generatorr
Series
-r
Datasheet

Specifications of ICS9FGP202AKLF

Input
Clock
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
40-VFQFN, 40-VFQFPN
Frequency-max
400MHz
Number Of Elements
3
Supply Current
200mA
Pll Input Freq (min)
25MHz
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
VFQFPN EP
Output Frequency Range
25 to 400MHz
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (max)
3.465V
Operating Temperature Classification
Commercial
Pin Count
40
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
9FGP202AKLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS9FGP202AKLFT
Quantity:
242
1339C—09/14/09
SMBus Table: CPU Frequency Select and Spread Spectrum Control Register
SMBus Table: RMII Output Control Register
SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register
SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register
SMBus Table: RMII Strength Control Register
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Integrated
Circuit
Systems, Inc.
Pin #
Pin #
Pin #
Pin #
Pin #
7,8
3,4
24
25
28
29
32
33
36
37
22
17
16
13
24
25
28
29
32
33
36
37
6
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DOT96SS PD Drive Mode
CPUCLK PD Drive Mode
32.768kHz Enable
33.33MHz Enable
DOT96SS Enable
25MHz_1 Enable
25MHz_0 Enable
CPUCLK Enable
DOT96 SS_EN
DOT96SS FS3
DOT96SS FS2
DOT96SS FS1
DOT96SS FS0
RMII_7 Enable
RMII_6 Enable
RMII_5 Enable
RMII_4 Enable
RMII_3 Enable
RMII_2 Enable
RMII_1 Enable
RMII_0 Enable
CPU SS_EN
RMII_7 Str
RMII_6 Str
RMII_5 Str
RMII_4 Str
RMII_3 Str
RMII_2 Str
RMII_1 Str
RMII_0 Str
Reserved
Reserved
Reserved
CPU FS2
CPU FS1
CPU FS0
Reserved
Reserved
Reserved
Reserved
Name
Name
Name
Name
Name
DOT96 Spread Spectrum Enable
CPU Spread Spectrum Enable
32.768KHz Output Control
33.33MHz Output Control
DOT96SS Output Control
25MHz_1 Output Control
25MHz_0 Output Control
DOT96 Freq Select Bit 3
DOT96 Freq Select Bit 2
DOT96 Freq Select Bit 1
DOT96 Freq Select Bit 0
CPUCLK Output Control
RMII_7 Strength Control
RMII_6 Strength Control
RMII_5 Strength Control
RMII_4 Strength Control
RMII_3 Strength Control
RMII_2 Strength Control
RMII_1 Strength Control
RMII_0 Strength Control
CPU Freq Select Bit 2
CPU Freq Select Bit 1
CPU Freq Select Bit 0
RMII_7 Output Control
RMII_6 Output Control
RMII_5 Output Control
RMII_4 Output Control
RMII_3 Output Control
RMII_2 Output Control
RMII_1 Output Control
RMII_0 Output Control
Control Function
Control Function
Control Function
Control Function
Control Function
Driven in PD
Driven in PD
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
13
Rev 0.20
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CPU Frequency Selection Table
DOT Frequency Selection Table
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
1-Load (1X)
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Driven
Driven
0
0
0
0
0
See Table 1:
See Table 2:
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ICS9FGP202A
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
2-Loads (2X)
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Hi-Z
Hi-Z
1
1
1
1
1
PWD
PWD
PWD
PWD
PWD
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

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