ICS9DB1200CGLF IDT, Integrated Device Technology Inc, ICS9DB1200CGLF Datasheet - Page 11
![IC BUFFER 12OUTPUT DIFF 64-TSSOP](/photos/40/58/405878/64-tfsop_sml.jpg)
ICS9DB1200CGLF
Manufacturer Part Number
ICS9DB1200CGLF
Description
IC BUFFER 12OUTPUT DIFF 64-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Bufferr
Series
-r
Datasheet
1.ICS9DB1200CGLFT.pdf
(14 pages)
Specifications of ICS9DB1200CGLF
Input
Differential
Output
Differential
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9DB1200CGLF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS9DB1200CGLF
Manufacturer:
IDT
Quantity:
124
Part Number:
ICS9DB1200CGLF
Manufacturer:
IDT
Quantity:
20 000
Part Number:
ICS9DB1200CGLFT
Manufacturer:
IDT
Quantity:
20 000
IDT
SMBus Table: Frequency Select Register
SMBus Table: Output Control Register
SMBus Table: Output Control Register
SMBus Table: Output Enable Readback
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICS9DB1200C
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
TM
Byte 0
Byte 1
Byte 2
Byte 3
/ICS
TM
Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM
43,42
38,37
27,28
22,23
19,20
14,15
11,12
58,59
53,54
50,51
45,46
43,42
38,37
27,28
22,23
19,20
14,15
11,12
6,7
6,7
-
-
-
-
-
-
-
-
-
-
-
-
Pin #
Pin #
Pin #
Pin #
BYPASS#/PLL
HIGH_BW#
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DIF_11
DIF_10
Name
Name
DIF_7
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Name
DIF_9
DIF_8
Name
OE7#
OE6#
OE5#
OE4#
OE3#
OE2#
OE1#
OE0#
FS2
FS1
FS0
Bypass (non-PLL Mode) or PLL Mode
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Output Control (Disable = Hi-Z)
Frequency Select 2
Frequency Select 1
Frequency Select 0
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
OE# Pin Readback
Control Function
Control Function
Control Function
Control Function
High or Low BW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
11
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
High BW
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Bypass
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Disable
0
See FS Table
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Low BW
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PLL
1
1
1
1
1414E—11/04/09
Latch
Latch
Latch
Latch
Latch
PWD
PWD
PWD
PWD
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1