SI5368B-C-GQR Silicon Laboratories Inc, SI5368B-C-GQR Datasheet - Page 12

• Manufacturer Part Number: SI5368B-C-GQR
• Description: IC CLK MULTIPLIER ATTEN 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5368B-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5368
12
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.
Pin #
13
57
16
17
21
29
30
32
42
FS_ALIGN
Pin Name
CS0_C3A
CS1_C4A
CKIN4+
CKIN4–
RATE0
RATE1
XA
XB
I/O
I/O
Table 3. Si5368 Pin Descriptions (Continued)
I
I
I
I
Signal Level
LVCMOS
ANALOG
LVCMOS
3-Level
MULTI
Preliminary Rev. 0.41
Input Clock Select/CKIN3 or CKIN4 Active Clock Indicator.
Input: If manual clock selection is chosen, and if
CKSEL_PIN = 1, the CKSEL pins control clock selection and
the CKSEL_REG bits are ignored.
If CKSEL_PIN = 0, the CKSEL_REG register bits control this
function and these inputs tristate. If configured as inputs, these
pins must not float.
Output: If auto clock selection is enabled, then they serve as
the CKIN_n active clock indicator.
0 = CKIN3 (CKIN4) is not the active input clock
1 = CKIN3 (CKIN4) is currently the active input to the PLL
The CKn_ACTV_REG bit always reflects the active clock status
for CKIN_n. If CKn_ACTV_PIN = 1, this status will also be
reflected on the CnA pin with active polarity controlled by the
CK_ACTV_POL bit. If CKn_ACTV_PIN = 0, this output tristates.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use inter-
nal oscillator based reference. Refer to Family Reference Man-
ual for interfacing to an external reference. External reference
must be from a high-quality clock source (TCXO, OCXO). Fre-
quency of crystal or external clock is set by the RATE pins.
FSYNC Alignment Control.
If FSYNC_ALIGN_PIN = 1 and CK_CONFIG = 1, a logic high
on this pin causes the FS_OUT phase to be realigned to the ris-
ing edge of the currently active input sync (CKIN_3 or CKIN_4).
If FSYNC_ALIGN_PIN = 0, this pin is ignored and the
FSYNC_ALIGN_REG bit performs this function.
0 = No realignment.
1 = Realign.
This pin has a weak pull-down.
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input associ-
ated with the CKIN2 clock when CK_CONFIG_REG = 1.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have both
a weak pull-up and a weak pull-down; they default to M.
CS[1:0]
00
01
10
11
Description
Active Input Clock
CKIN1
CKIN2
CKIN3
CKIN4