SI5020-BM Silicon Laboratories Inc, SI5020-BM Datasheet - Page 6

• Manufacturer Part Number: SI5020-BM
• Description: IC CLOCK/DATA RECOVERY 20MLP
• Manufacturer: Silicon Laboratories Inc
• Type: Clock and Data Recovery (CDR)r

Specifications of SI5020-BM

• Package / Case: 20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
• Input: Differential
• Output: CML
• Frequency - Max: 2.7GHz
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 2.7GHz
• Product: RF / Wireless
• Supply Current: 122 mA
• Maximum Operating Temperature: 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1128

Table 2. DC Characteristics
(V
Parameter
Supply Current
OC-48 and FEC (2.7 GHz)
GbE
OC-12
OC-3
Power Dissipation
OC-48 and FEC (2.7 GHz)
GbE
OC-12
OC-3
Common Mode Input Voltage
(DIN, REFCLK)*
Single-Ended Input Voltage (DIN, REFCLK)*
Differential Input Voltage Swing
(DIN, REFCLK)*
Input Impedance (DIN, REFCLK)*
Differential Output Voltage Swing (DOUT)
OC48/12/3
Differential Output Voltage Swing (CLKOUT)
OC48/12/3
Output Common Mode Voltage
(DOUT,CLKOUT)
Output Impedance (DOUT,CLKOUT)
Output Short to GND (DOUT,CLKOUT)
Output Short to V
Input Voltage Low (LVTTL Inputs)
Input Voltage High (LVTTL Inputs)
Input Low Current (LVTTL Inputs)
Input High Current (LVTTL Inputs)
Output Voltage Low (LVTTL Outputs)
Output Voltage High (LVTTL Outputs)
Input Impedance (LVTTL Inputs)
PWRDN/CAL Leakage Current
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
Si5020
6
DD
= 2.5 V ±5%, T
swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID
min) and the unused input must be ac coupled to ground. When driving differentially, the difference between the positive
and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (VIS max).
DD
A
= –40 to 85 °C)
(DOUT,CLKOUT)
Symbol
I
PWRDN
V
R
I
I
V
V
V
SC(–)
SC(+)
V
V
I
V
V
R
V
R
V
P
OCM
I
OUT
I
DD
ICM
OD
OD
IH
OH
IL
OL
IS
ID
IN
IH
IN
IL
D
Rev. 1.4
V
Test Condition
varies with V
Single-ended
PWRDN
See Figure 1
See Figure 1
Line-to-Line
Line-to-Line
Line-to-Line
Line-to-Line
100 Ω Load
100 Ω Load
100 Ω Load
I
I
O
O
= 2 mA
= 2 mA
≥ 0.8 V
DD
–17.5
Min
200
200
780
550
2.0
2.0
84
84
10
15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
.80 x V
V
–14.5
0.23
Typ
108
113
117
124
270
283
293
310
100
990
900
100
DD
25
25
—
—
—
—
—
—
—
—
—
–
DD
1500
1260
1260
Max
122
127
131
138
320
333
344
362
750
116
116
0.4
31
10
10
35
—
—
—
—
—
—
.8
mV
mV
mV
mV
Unit
mW
mA
mA
mA
µ A
µ A
k Ω
µ A
Ω
Ω
V
V
V
V
V
V
PP
PP
PP
PP