ICS85320AMILF IDT, Integrated Device Technology Inc, ICS85320AMILF Datasheet
ICS85320AMILF
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85320AMILF
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ICS85320AMILF Summary of contents
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LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR G D ENERAL ESCRIPTION The ICS85320I is a LVCMOS / LVTTL-to-Differen tial 3.3V, 2.5V LVPECL translator and a member HiPerClockS™ of the HiPerClocks™ family of High Performance Clocks Solutions from IDT. The ICS85320I ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR ABLE IN ESCRIPTIONS ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, JA Storage Temperature, T -65°C to ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR T 4A 3.3V±5%, T ABLE HARACTERISTICS ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR P ARAMETER LVPECL V EE -1.3V ± 0.165V 3.3V C /3. ORE UTPUT OAD EST Part 1 nQx Qx Part 2 nQy Qy t sk( ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR T 2.5V LVPECL O ERMINATION FOR Figure 2A and Figure 2B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 2V. For V = 2.5V, ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR PPLICATION CHEMATIC XAMPLE Figure 3 shows an example of ICS85320I application schematic. In this example, the device is operated at V capacitor should be located as close as possible to the ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR This section provides information on power dissipation and junction temperature for the ICS85320I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85320I is the sum of ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure calculate worst case ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR ABLE VS IR LOW ABLE FOR JA Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR ACKAGE UTLINE UFFIX FOR IDT ™ / ICS ™ 3.3V, 2.5V LVPECL TRANSLATOR SOIC EAD ABLE ACKAGE IMENSIONS ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR ABLE RDERING NFORMATION ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR ...
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ICS85320I LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 ...