ICS8534AY-01LF IDT, Integrated Device Technology Inc, ICS8534AY-01LF Datasheet - Page 13
![IC FANOUT BUFFER LVPECL 64-TQFP](/photos/6/51/65144/ics8534ay-01lf_sml.jpg)
ICS8534AY-01LF
Manufacturer Part Number
ICS8534AY-01LF
Description
IC FANOUT BUFFER LVPECL 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
HiPerClockS™r
Type
Fanout Buffer (Distribution), Multiplexerr
Datasheet
1.ICS8534AY-01LF.pdf
(21 pages)
Specifications of ICS8534AY-01LF
Number Of Circuits
1
Ratio - Input:output
2:22
Differential - Input:output
Yes/Yes
Input
CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVPECL
Frequency - Max
500MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Frequency-max
500MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1173
8534AY-01LF
8534AY-01LF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ICS8534AY-01LF
Manufacturer:
IDT
Quantity:
83
Company:
Part Number:
ICS8534AY-01LF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
ICS8534AY-01LFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
ICS8534-01 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
Figure 5A. 3.3V LVPECL Output Termination
ICS8534AY-01 REVISION B MARCH 28, 2011
RTT =
((V
3.3V
OH
LVPECL
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50Ω
= 50Ω
* Z
R1
50Ω
o
RTT
R2
50Ω
V
+
_
CC
3.3V
- 2V
Input
Ω
13
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 5B. 3.3V LVPECL Output Termination
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
3.3V
LVPECL
Z
Z
o
o
= 50Ω
= 50Ω
R3
125Ω
©2011 Integrated Device Technology, Inc.
R1
84Ω
3.3V
R4
125Ω
R2
84Ω
+
_
3.3V
Input