ICS558G-01LF IDT, Integrated Device Technology Inc, ICS558G-01LF Datasheet - Page 2

• Manufacturer Part Number: ICS558G-01LF
• Description: IC CLK DVR PECL/CMOS 16-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr
• Series: ClockBlocks™r

Specifications of ICS558G-01LF

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/No
• Input: CMOS, PECL
• Output: 3-State, CMOS
• Frequency - Max: 250MHz
• Voltage - Supply: 2.375 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 250MHz
• Number Of Clock Inputs: 2
• Output Logic Level: CMOS
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Signal Type: CMOS/PECL
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 558G-01LF

Pin Assignment
Pin Descriptions
IDT™ / ICS™ PECL/CMOS TO CMOS CLOCK DRIVER
ICS558-01
PECL/CMOS TO CMOS CLOCK DRIVER
Number
Pin
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
CMOSIN
PECLIN
PECLIN
VDDP
GND
OE0
SELPECL
S0
S1
CMOSIN
PECLIN
PECLIN
Name
VDDP
VDDC
CLK4
CLK3
CLK2
CLK1
GND
GND
OE0
OE1
Pin
16-pin 173 Mil (0.65mm) TSSOP
S0
S1
1
2
3
4
5
6
7
8
Clock Input
Clock Input
Clock Input
Pin Type
Output
Output
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
16
15
14
13
12
11
10
9
SELPECL
VDDC
CLK1
CLK2
CLK3
CLK4
GND
OE1
Select 0 for output divider. See table above. Internal pull-up to VDDP.
Select 1 for output divider. See table above. Internal pull-up to VDDP.
Connect to +3.3 V or +5 V. Decouple to pin 6.
PECL input. Connect to ground if not used.
Complimentary PECL input. Connect to ground if not used.
Connect to ground.
CMOS input. Connect to ground if not used.
Output Enable 0. See table above. Internal pull-up to VDDP.
Output Enable 1. See table above. Internal pull-up to VDDP.
Connect to ground.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Low skew clock output.
Connect to +2.5 V, +3.3 V, or +5 V. Decouple to pin 10.
Selects PECL or CMOS input. See table above. Internal pull-up to
VDDP.
2
Input Clock Selection
Tri-State Table
Output Divide Selection
Pin Description
OE1 OE0
SELPECL
S1
0
0
1
1
0
0
1
1
0
1
S0
0
1
0
1
0
1
0
1
Output Divide
Clock ON
Clock ON
CMOSIN
PECLIN
Tri-state
Tri-state
CLK 1
Input
/1
/2
/3
/4
ICS558-01
PECL CLOCK DRIVER
CLK 2, 3, 4
Clock ON
Clock ON
Tri-state
Tri-state
REV F 051310