MPC9447AC IDT, Integrated Device Technology Inc, MPC9447AC Datasheet - Page 5

• Manufacturer Part Number: MPC9447AC
• Description: IC CLK FANOUT BUFFER 1:9 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MPC9447AC

• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Input: LVCMOS
• Output: LVCMOS
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS
• Mounting: Surface Mount
• Pin Count: 32
• Quiescent Current: 2mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC9447 Data Sheet
Table 8. AC Characteristics (V
MPC9447 REVISION 6 APRIL 13, 2010
1. AC characteristics apply for parallel output termination of 50 Ω to V
2. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
3. Setup and hold times are referenced to the falling edge of the selected clock signal input.
4. Output pulse skew is the absolute difference of the propagation delay times: | t
Symbol
t
t
t
f
PLZ, HZ
PZL, ZH
t
PLH/HL
t
t
P,REF
sk(PP)
DC
output duty cycle and maximum frequency specifications.
f
SK(P)
t
sk(O)
t
t
f
max
r
r
t
JIT
t
ref
, t
, t
S
H
Q
f
f
Input Frequency
Output Frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
Propagation Delay
Output Disable Time
Output Enable Time
Setup Time
Hold Time
Output-to-Output Skew
Device-to-Device Skew
Ouput Pulse Skew
Output Duty Cycle
Output Rise/Fall Time
Buffer Additive Phase Jitter, RMS
(4)
Characteristics
CC
CCLK0 or CCLK1 to CLK_STOP
CCLK0 or CCLK1 to CLK_STOP
= 2.5 V ± 5%, T
CCLK0 or CCLK1 to any Q
A
= -40 C to +85 C)
f
Q
<350 MHz
(3)
(3)
TT
.
Min
1.4
1.7
0.0
1.0
0.1
45
5
0
0
(1)
PLH
– t
PHL
0.03
Typ
50
|.
1.0
Max
350
350
150
200
4.4
2.7
1.0
11
11
55
(2)
3.3V, 2.5V, 1:9 LVCMOS CLOCK FANOUT BUFFER
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ps
ns
ps
ns
ps
%
©2010 Integrated Device Technology, Inc.
0.7 to 1.7 V
DC
0.6 to 1.8 V
156.25MHz,
Integration Range:
12kHz - 20MHz
REF
= 50%
Condition