MPC9447AC IDT, Integrated Device Technology Inc, MPC9447AC Datasheet - Page 6

• Manufacturer Part Number: MPC9447AC
• Description: IC CLK FANOUT BUFFER 1:9 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of MPC9447AC

• Number Of Circuits: 1
• Ratio - Input:output: 2:9
• Differential - Input:output: No/No
• Input: LVCMOS
• Output: LVCMOS
• Frequency - Max: 350MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 350MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Single-Ended
• Output Frequency: 350MHz
• Output Logic Level: LVCMOS
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Signal Type: LVCMOS
• Mounting: Surface Mount
• Pin Count: 32
• Quiescent Current: 2mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC9447 Data Sheet
Driving Transmission Lines
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user, the output drivers were designed
to exhibit the lowest impedance possible. With an output impedance
of 17 Ω (V
terminated transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note AN1091.
In most high performance clock networks, point-to-point distribution
of signals is the method of choice. In a point-to-point scheme, either
series terminated or parallel terminated transmission lines can be
used. The parallel technique terminates the signal at the end of the
line with a 50 Ω resistance to V
only a single terminated line can be driven by each output of the
MPC9447 clock driver. For the series terminated case, however,
there is no DC current draw; thus, the outputs can drive multiple
series terminated lines.
series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9447 clock driver
is effectively doubled due to its capability to drive multiple lines at
V
MPC9447 REVISION 6 APRIL 13, 2010
CLK_STOP
CC
CCLK0 or
Q0 to Q8
IN
IN
The MPC9447 clock driver was designed to drive high-speed
This technique draws a fairly high level of DC current, and thus,
CCLK1
= 3.3 V.
Figure 4. Single versus Dual Transmission Lines
MPC9447
MPC9447
CC
Output
Output
Buffer
Buffer
17Ω
17Ω
Figure 3. Output Clock Stop (CLK_STOP)
= 3.3 V), the outputs can drive either parallel or series
Figure 4
R
R
R
S
Timing Diagram
S
S
= 33Ω
= 33Ω
= 33Ω
CC
illustrates an output driving a single
÷2.
Z
Z
Z
O
O
O
= 50Ω
= 50Ω
= 50Ω
APPLICATION INFORMATION
OutA
OutB0
OutB1
6
output driving a single line versus two lines. In both cases, the drive
capability of the MPC9447 output buffer is more than sufficient to
drive 50 Ω transmission lines on the incident edge. Note from the
delay measurements in the simulation,s a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9447. The output waveform in
Figure 5
impedance mismatch seen looking into the driver. The parallel
combination of the 33 Ω series resistor, plus the output impedance,
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
reflection coefficient, to 2.5 V. It will then increment towards the
quiescent 3.0 V in steps separated by one round trip delay (in this
case 4.0 ns).
The waveform plots in
At the load end, the voltage will double, due to the near unity
3.0
2.5
2.0
1.5
1.0
0.5
0
shows a step in the waveform; this step is caused by the
t
D
2
V
Z
R
R
V
= 3.8956
OutA
0
Figure 5. Single versus Dual Line
L
S
0
L
In
= V
= 50 Ω || 50 Ω
= 33 Ω || 33 Ω
= 17 Ω
= 3.0 (25 ÷ (16.5+17+25)
= 1.28 V
4
Termination Waveforms
S
(Z
3.3V, 2.5V, 1:9 LVCMOS CLOCK FANOUT BUFFER
Figure 5
0
÷ (R
6
Time (ns)
t
S
D
+R
©2010 Integrated Device Technology, Inc.
= 3.9386
OutB
show the simulation results of an
8
0
+Z
0
))
10
12
14