ICS85304AG-01LF IDT, Integrated Device Technology Inc, ICS85304AG-01LF Datasheet - Page 2

• Manufacturer Part Number: ICS85304AG-01LF
• Description: IC FANOUT BUFFER 1-5 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85304AG-01LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85304AG-01LF

Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
Symbol
C
R
R
11, 18, 20
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Number
IN
PULLDOWN
PULLUP
9, 10
1, 2
3, 4
5, 6
7, 8
12
13
14
15
16
17
19
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
CLK_SEL
CLK_EN
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
nCLK0
nCLK1
Name
CLK0
CLK1
V
V
CC
EE
Output
Output
Output
Output
Output
Power
Power
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Test Conditions
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Positive supply pins.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Negative supply pin.
Non-inverting differential clock input.
Inverting differential clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH.
LVTTL/LVCMOS interface levels.
2
Minimum
Typical
ICS85304AG-01 REV. E JULY 8, 2008
51
51
4
Maximum
Units
k
k
pF
Ω
Ω