ICS85304AG-01LF IDT, Integrated Device Technology Inc, ICS85304AG-01LF Datasheet - Page 9

• Manufacturer Part Number: ICS85304AG-01LF
• Description: IC FANOUT BUFFER 1-5 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85304AG-01LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85304AG-01LF

Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to
ground.
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
Figure 3A. 3.3V LVPECL Output Termination
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
RTT =
((V
FOUT
OH
+ V
OL
) / (V
1
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
Z
o
50
RTT
50
V
CC
FIN
- 2V
9
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 3B. 3.3V LVPECL Output Termination
FOUT
Z
Z
o
o
= 50
= 50
ICS85304AG-01 REV. E JULY 8, 2008
125
84
3.3V
125
84
FIN