ICS85304AG-01LF IDT, Integrated Device Technology Inc, ICS85304AG-01LF Datasheet - Page 8

• Manufacturer Part Number: ICS85304AG-01LF
• Description: IC FANOUT BUFFER 1-5 20-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS85304AG-01LF

• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVPECL
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 85304AG-01LF

Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
V
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
Figure 2A. HiPerClockS CLK/nCLK Input
Figure 2C. HiPerClockS CLK/nCLK Input
Figure 2E. HiPerClockS CLK/nCLK Input
IDT™ / ICS™ 3.3V LVPECL FANOUT BUFFER
PP
ICS85304-01
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
and V
2.5V
1.8V
3.3V
HCSL
LVPECL
CMR
*Optional – R3 and R4 can be 0
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V HCSL Driver
input requirements. Figures 2A to 2F show interface
*R3
*R4
Zo = 50
Zo = 50
Zo = 50
Zo = 50
33
33
Zo = 50
Zo = 50
R3
125
R1
50
3.3V
SWING
R1
84
R1
50
R4
125
R2
50
R2
84
and V
R2
50
CLK
nCLK
CLK
nCLK
OH
CLK
nCLK
3.3V
3.3V
must meet the
3.3V
HiPerClockS
Input
HiPerClockS
Input
HiPerClockS
Input
8
component to confirm the driver termination requirements. For
example, in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 2B. HiPerClockS CLK/nCLK Input
Figure 2D. HiPerClockS CLK/nCLK Input
Figure 2F. HiPerClockS CLK/nCLK Input
2.5V
3.3V
3.3V
SSTL
LVDS
LVPECL
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
Driven by a 2.5V SSTL Driver
Zo = 60
Zo = 60
Zo = 50
Zo = 50
Zo = 50
Zo = 50
ICS85304AG-01 REV. E JULY 8, 2008
R3
120
2.5V
R1
120
R1
50
R2
50
R4
120
R2
120
R2
50
R1
100
CLK
nCLK
CLK
nCLK
CLK
nCLK
3.3V
3.3V
HiPerClockS
3.3V
HiPerClockS
Input
Receiver