ICS8534BMI-13LFT IDT, Integrated Device Technology Inc, ICS8534BMI-13LFT Datasheet - Page 11

• Manufacturer Part Number: ICS8534BMI-13LFT
• Description: IC FANOUT BUFFER 1-4 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Buffer (Distribution), Multiplexerr

Specifications of ICS8534BMI-13LFT

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: No/Yes
• Input: LVCMOS, LVTTL, Crystal
• Output: LVCMOS, LVPECL
• Frequency - Max: 266MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Frequency-max: 266MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8534BMI-13LFT

LVCMOS
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure X. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
T
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
IDT
RTT =
ERMINATION FOR
ICS8534I-13
1-TO-4, CRYSTAL OSCILLATOR/LVCMOS-TO-3.3V LVPECL/LVCMOS FANOUT BUFFER
™
/ ICS
((V
F
™
FOUT
OH
IGURE
3.3V LVPECL/LVCMOS FANOUT BUFFER
+ V
TO
OL
XTAL I
4A. LVPECL O
) / (V
1
LVPECL O
CC
Z
Z
– 2)) – 2
o
o
= 50
= 50
NTERFACE
F
IGURE
Z
o
50
UTPUT
UTPUTS
3. G
VDD
Ro
T
ENERAL
RTT
ERMINATION
50
V
CC
D
IAGRAM FOR
FIN
- 2V
Rs
Zo = Ro + Rs
Zo = 50
LVCMOS D
11
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
and R2 can be 100 . This can also be accomplished by removing
R1 and making R2 50 .
50
be used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
VDD
transmission lines. Matched impedance techniques should
RIVER TO
FOUT
R1
R2
F
IGURE
.1uf
XTAL I
4B. LVPECL O
XTAL_IN
XTAL_OUT
Z
Z
o
o
NPUT
= 50
= 50
I
125
NTERFACE
84
ICS8534BMI-13 REV. B MAY 16, 2008
UTPUT
3.3V
125
84
T
ERMINATION
FIN
PRELIMINARY
applications, R1