ICS8543BGI IDT, Integrated Device Technology Inc, ICS8543BGI Datasheet - Page 6

• Manufacturer Part Number: ICS8543BGI
• Description: IC CLK FAN BUFF MUX 1:4 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8543BGI

• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 650MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 650MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 650MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 8543BGI

AC Electrical Characteristics
Table 5. AC Characteristics, V
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the differential output cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVDS FANOUT BUFFER
Parameter
f
tjit
t
tsk(o)
tsk(pp)
t
odc
MAX
PD
R
ICS8543I
LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
/ t
F
Symbol
Maximum Output Frequency
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
DD
= 3.3V ± 5%, T
odc
A
153.6MHz, Integration Range:
= -40°C to 85°C
20% to 80% @ 50MHz
Test Conditions
12kHz – 20MHz
ƒ ≤ 650MHz
6
Minimum
150
1.5
45
ICS8543BGI REV. E SEPTEMBER 9, 2008
Typical
0.164
50
Maximum
650
600
450
2.6
40
55
Units
MHz
ps
ps
ns
ps
ps
%