MAX9312ECJ+ Maxim Integrated Products, MAX9312ECJ+ Datasheet - Page 7

• Manufacturer Part Number: MAX9312ECJ+
• Description: IC DVR CLK/DATA DUAL 1:5 32LQFP
• Manufacturer: Maxim Integrated Products
• Type: Fanout Buffer (Distribution), Datar

Specifications of MAX9312ECJ+

• Number Of Circuits: 2
• Ratio - Input:output: 1:5
• Differential - Input:output: Yes/Yes
• Input: HSTL, LVECL, LVPECL
• Output: LVECL, LVPECL
• Frequency - Max: 3GHz
• Voltage - Supply: 2.25 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 3GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX9312/MAX9314 are low-skew, dual 1-to-5 differ-
ential drivers designed for clock and data distribution.
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distribu-
tion in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
The differential inputs can be configured to accept sin-
gle-ended inputs when operating at approximately V
V
to 3.8V for the MAX9314. This is accomplished by con-
necting the on-chip reference voltage, V
as a reference. For example, the differential CLKA, CLKA
input is converted to a noninverting, single-ended input
by connecting V
ended input to CLKA. Similarly, an inverting input is
obtained by connecting V
the single-ended input to CLKA. With a differential input
configured as single ended (using V
ended input can be driven to V
gle-ended LVPECL/LVECL signal.
When a differential input is configured as a single-ended
input (using V
V
2.7V to 3.8V for the MAX9314. This is because one of the
inputs must be V
of the input stage. V
because it becomes the high-level input when the other
(single-ended) input swings below it. Therefore, mini-
mum V
The minimum V
1.525V and the minimum V
V
each device into V
supply of 2.725V for the MAX9312 and 2.58V for the
MAX9314. Rounding up to standard supplies gives the
single-ended operating supply ranges of V
3.0V to 3.8V for the MAX9312 and V
3.8V for the MAX9314.
When using the V
0.01µF ceramic capacitor to V
not used, it can be left open. The V
source or sink 0.5mA, which is sufficient to drive two
inputs. Use V
device as the V
The maximum magnitude of the differential input from
CLK_ to CLK_ is 3.0V or V
EE
EE
CC
= 3.0V to 3.8V for the MAX9312 or V
= 3.0V to 3.8V for the MAX9312 and V
- 1.38V. Substituting the minimum V
BB
= V
BB
EE
BB
BB
), the approximate supply range is V
Dual 1:5 Differential LVPECL/LVECL/HSTL
BB
+ 1.2V.
EE
BB
only for inputs that are on the same
BB
reference.
_______________________________________________________________________________________
BB
+ 1.2V or higher for proper operation
to CLKA and connecting the single-
output for the MAX9312 is V
reference output, bypass it with a
= V
BB
Detailed Description
EE
must be at least V
BB
BB
CC
+ 1.2V results in a minimum
CC
output for the MAX9314 is
to CLKA and connecting
CC
- V
. If the V
EE
and V
, whichever is less.
CC
BB
BB
CC
EE
- V
BB
BB
reference can
), the single-
BB
or with a sin-
, to an input
EE
- V
reference is
CC
CC
EE
output for
EE
= 2.7V to
- V
- V
+ 1.2V
= 2.7V
EE
EE
CC
CC
CC
=
=
-
-
-
Clock and Data Drivers
This limit also applies to the difference between any ref-
erence voltage input and a single-ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting inputs (CLKA and CLKB) are biased with a
75kΩ pullup to V
noninverting inputs (CLKA and CLKB) are biased with a
75kΩ pulldown to V
Specifications for the high and low voltages of a differen-
tial input (V
age (V
higher than V
Output levels are referenced to V
LVPECL or LVECL, depending on the level of the V
supply. With V
V
outputs are LVECL when V
V
A single-ended input of at least V
tial input of at least 95mV switches the outputs to the
V
Characteristics table.
Bypass V
ceramic 0.1µF and 0.01µF capacitors in parallel as close
to the device as possible, with the 0.01µF value capaci-
tor closest to the device. Use multiple parallel vias for
low inductance. When using the V
bypass it with a 0.01µF ceramic capacitor to V
V
Input and output trace characteristics affect the perfor-
mance of the MAX9312/MAX9314.
Connect each signal of a differential input or output to a
50Ω characteristic impedance trace. Minimize the num-
ber of vias to prevent impedance discontinuities. Reduce
reflections by maintaining the 50Ω characteristic imped-
ance through connectors and across cables. Reduce
skew within a differential pair by matching the electrical
length of the traces.
Terminate outputs through 50Ω to V
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if QA0 is used as a single-ended
output, terminate both QA0 and QA0.
EE
EE
BB
OH
is connected to a negative supply.
reference is not used, it can be left open).
connected to GND, the outputs are LVPECL. The
and V
IHD
CC
- V
IHD
OL
IHD
to V
ILD
CC
and V
levels specified in the DC Electrical
Applications Information
).
) apply simultaneously (V
CC
EE
connected to a positive supply and
EE
with high-frequency surface-mount
and a 75kΩ pulldown to V
.
ILD
) and the differential input volt-
CC
is connected to GND and
Output Termination
BB
CC
Supply Bypassing
BB
±95mV or a differen-
and are considered
CC
reference output,
- 2V or use an
ILD
cannot be
CC
Traces
EE
(if the
. The
CC
7