MPC9449AE Freescale Semiconductor, MPC9449AE Datasheet

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MPC9449AE

Manufacturer Part Number
MPC9449AE
Description
IC CLOCK FANOUT BUFF 1:15 52LQFP
Manufacturer
Freescale Semiconductor
Type
Fanout Buffer (Distribution), Divider, Multiplexerr
Datasheet

Specifications of MPC9449AE

Number Of Circuits
1
Ratio - Input:output
3:15
Differential - Input:output
Yes/No
Input
LVCMOS, LVPECL
Output
LVCMOS
Frequency - Max
200MHz
Voltage - Supply
2.375 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
52-LQFP
Frequency-max
200MHz
Supply Voltage Max
2.5V
Package/case
52-LQFP
Leaded Process Compatible
Yes
Logic Type
LVPECL Or LVCMOS
Peak Reflow Compatible (260 C)
Yes
Supply Voltage Min
3.3V
Rohs Compliant
Yes
Operating Temperature Range
-40°C To +85°C
No. Of Multipliers / Dividers
2
Frequency
200MHz
Digital Ic Case Style
TQFP
Supply Current
10mA
Clock Ic Type
Clock Buffer
No. Of Outputs
15
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC9449AE
Manufacturer:
Freescale
Quantity:
160
Part Number:
MPC9449AE
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
MPC9449AER2
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3.3V/2.5V 1:15 PECL/LVCMOS
Clock Fanout Buffer
targeted for high performance clock tree applications. With output
frequencies up to 200 MHz and output skews less than 200 ps the device
meets the needs of the most demanding clock applications.
Features
Functional Description
compatible clock signals up to a frequency of 200 MHz. The device has
15 identical outputs, organized in 4 output banks. Each output bank
provides a retimed or frequency divided copy of the input signal with a
near zero skew. The output buffer supports driving of 50
transmission lines on the incident edge: each output is capable of driving
either one parallel terminated or two series terminated transmission lines.
addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input
reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the
OE control will force the outputs into high-impedance mode.
2.5V or 3.3V power supply and an ambient temperature range of –40 C to +85 C. The MPC9449 is pin and function compatible
but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
15 LVCMOS compatible clock outputs
Two selectable LVCMOS and one differential LVPECL compatible clock
inputs
Selectable output frequency divider (divide-by-one and divide-by-two)
Maximum clock frequency of 200 MHz
Maximum clock skew of 200 ps
High-impedance output control
3.3V or 2.5V power supply
Drives up to 30 series terminated clock lines
Ambient temperature range –40 C to +85 C
52 lead LQFP packaging
Supports clock distribution in networking, telecommunication and
computing applications
Pin and function compatible to MPC949
The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer
The MPC9449 is specifically designed to distribute LVCMOS
Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In
All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a
Motorola, Inc. 2002
1
terminated
CLOCK FANOUT BUFFER
52 LEAD LQFP PACKAGE
MPC9449
PECL/LVCMOS
3.3V/2.5V 1:15
CASE 848D
FA SUFFIX
Order Number: MPC9449/D
Rev 1, 08/2002

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MPC9449AE Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less ...

Page 2

MPC9449 DSELA V CC CCLK0 0 0 CCLK1 CCLK_SEL PCLK PCLK PCLK_SEL DSELB DSELC DSELD MR/OE Figure 1. MPC9449 Logic Diagram Table 1: FUNCTION TABLE Control Default PCLK_SEL 0 LVCMOS clock input selected (CCLK0 ...

Page 3

Table 3: GENERAL SPECIFICATIONS Symbol Characteristics V TT Output Termination Voltage MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch–Up Immunity C PD Power Dissipation Capacitance C IN Input Capacitance Table 4: ABSOLUTE MAXIMUM RATINGS a ...

Page 4

MPC9449 Table 5: DC CHARACTERISTICS ( 3.3V Symbol Characteristics V IH Input high voltage V IL Input low voltage V OH Output High Voltage V PP Peak-to-peak input voltage V CMR b Common Mode Range V OL Output ...

Page 5

Table 7: DC CHARACTERISTICS ( 2.5V Symbol Characteristics V IH Input high voltage V IL Input low voltage V PP Peak-to-peak input voltage V CMR a Common Mode Range V OH Output High Voltage V OL Output Low ...

Page 6

MPC9449 Driving Transmission Lines The MPC9449 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. ...

Page 7

MPC9449 DUT Pulse Generator Figure 6. CCLK MPC9449 AC test reference for 3.3V and 2.5V MPC9449 DUT ...

Page 8

MPC9449 t SK(O) The pin–to–pin skew is defined as the worst case difference in prop- agation delay between any similar delay path within a single device Figure 8. Output–to–output Skew t SK(O) PCLK V PP PCLK (LH) ...

Page 9

H L– VIEW Y 3X –L– –N– –H– –T– 3 SEATING 4X PLANE 0.05 (0.002 VIEW AA OUTLINE DIMENSIONS FA SUFFIX LQFP ...

Page 10

MPC9449 MOTOROLA NOTES 10 ...

Page 11

NOTES 11 MPC9449 MOTOROLA ...

Page 12

MPC9449 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out ...

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