MPC9449AE Freescale Semiconductor, MPC9449AE Datasheet - Page 2

• Manufacturer Part Number: MPC9449AE
• Description: IC CLOCK FANOUT BUFF 1:15 52LQFP
• Manufacturer: Freescale Semiconductor
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of MPC9449AE

• Number Of Circuits: 1
• Ratio - Input:output: 3:15
• Differential - Input:output: Yes/No
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Frequency - Max: 200MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-LQFP
• Frequency-max: 200MHz
• Supply Voltage Max: 2.5V
• Package/case: 52-LQFP
• Leaded Process Compatible: Yes
• Logic Type: LVPECL Or LVCMOS
• Peak Reflow Compatible (260 C): Yes
• Supply Voltage Min: 3.3V
• Rohs Compliant: Yes
• Operating Temperature Range: -40°C To +85°C
• No. Of Multipliers / Dividers: 2
• Frequency: 200MHz
• Digital Ic Case Style: TQFP
• Supply Current: 10mA
• Clock Ic Type: Clock Buffer
• No. Of Outputs: 15
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC9449
CCLK_SEL
PCLK_SEL
MOTOROLA
Table 1: FUNCTION TABLE
PCLK_SEL
CCLK_SEL
DSELA, DSELB,
DSELC, DSELD
MR/OE
Table 2: PIN CONFIGURATION
PCLK, PCLK
CCLK0, CCLK1
PCLK_SEL
CCLK_SEL
DSELA, DSELB, DSELC, DSELD
MR/OE
QA0-1, QB0-2, QC0-3, QD0-5
GND
VCC
DSELA
DSELB
DSELC
DSELD
MR/OE
CCLK0
CCLK1
PCLK
PCLK
Control
Figure 1. MPC9449 Logic Diagram
Pin
0
1
V CC
V CC
Default
0 0
0 0
0
0
1
0
1
LVCMOS clock input selected (CCLK0 or CCLK1)
1
2
Input
Input
Input
Input
Input
Input
Output
Supply
Supply
I/O
0
1
0
1
0
1
0
1
Outputs enabled
CCLK0 selected
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
Type
0
1
QA0
QA1
QB0
QB1
QB2
QC0
QC1
QC2
QC3
QD0
QD1
QD2
QD3
QD4
QD5
Differential LVPECL clock input
LVCMOS clock inputs
LVPECL clock input select
LVCMOS clock input select
Clock divider selection
Output enable/disable (high-impedance tristate)
Clock outputs
Negative power supply (GND)
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation
2
GND
GND
GND
GND
VCC
VCC
VCC
QB2
QB1
QB0
QA1
QA0
NC
Figure 2. MPC9449 52–Lead Package Pinout (Top View)
40
41
42
43
44
45
46
47
48
49
50
51
52
39 38 37 36 35 34 33 32 31 30 29 28 27
1
2
3
4
Outputs disabled (high impedance)
PCLK differential input selected
5
Function
MPC9449
6
CCLK1 selected
7
8
1
9 10 11 12 13
2
26
25
24
23
22
21
20
19
18
17
16
15
14
NC
VCC
QD4
GND
QD3
VCC
QD2
GND
QD1
VCC
QD0
GND
NC