ADF4154BRUZ Analog Devices Inc, ADF4154BRUZ Datasheet - Page 2

• Manufacturer Part Number: ADF4154BRUZ
• Description: IC FRAC-N FREQ SYNTH 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4154BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4154EBZ1 - BOARD EVALUATION FOR ADF4154EB1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4154
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Pin Configuration and Pin Function Descriptions...................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Registers ........................................................................................... 11
REVISION HISTORY
12/06—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to Functional Block Diagram.......................................... 1
Changes to Specifications ................................................................ 3
Changes to Absolute Maximum Ratings ....................................... 5
Changes to Typical Performance Characteristics Conditions .... 7
Replaced Figure 5 through Figure 7............................................... 7
Changes to Figure 13........................................................................ 8
Changes to R-Divider Register Map ............................................ 13
Changes to Control Register Map ................................................ 14
Change to REF
Added Initialization Sequence Section........................................ 18
Timing Characteristics ................................................................ 4
ESD Caution.................................................................................. 5
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
RF INT Divider............................................................................. 9
INT, FRAC, MOD, and R Relationship ..................................... 9
R-Counter...................................................................................... 9
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect...................................................... 10
Input Shift Registers ................................................................... 10
Program Modes .......................................................................... 10
IN
Doubler Section................................................ 18
Rev. A | Page 2 of 24
Outline Dimensions ....................................................................... 22
Change to 12-Bit Programmable Modulus Section ................... 18
Changes to Fast-Lock Timer and Register Sequences Section........19
Changes to Fast Lock: Loop Filter Topology Section ................ 19
Deleted Spurious Signal Section................................................... 18
Added Spur Mechanisms Section ................................................ 19
Added Spur Consistency Section ................................................. 20
Change to Filter Design—ADIsimPLL Section.......................... 20
Change to Interfacing Section ...................................................... 20
Updated Outline Dimensions....................................................... 22
Changes to Ordering Guide .......................................................... 22
5/04—Revision 0: Initial Version
Register Definitions ................................................................... 16
R-Divider Register, R1 ............................................................... 16
Control Register, R2................................................................... 16
Noise and Spur Register, R3...................................................... 17
Reserved Bits............................................................................... 17
Initialization Sequence .............................................................. 18
RF Synthesizer: A Worked Example ........................................ 18
Modulus....................................................................................... 18
Reference Doubler and Reference Divider ............................. 18
12-Bit Programmable Modulus................................................ 18
Spurious Optimization and Fast lock ...................................... 18
Fast-Lock Timer and Register Sequences ............................... 19
Fast Lock: An Example .............................................................. 19
Fast Lock: Loop Filter Topology............................................... 19
Spur Mechanisms ....................................................................... 19
Spur Consistency........................................................................ 20
Filter Design—ADIsimPLL....................................................... 20
Interfacing ................................................................................... 20
PCB Design Guidelines for Chip Scale Package .................... 21
Ordering Guide .......................................................................... 22