ADF4154BRUZ Analog Devices Inc, ADF4154BRUZ Datasheet - Page 9

• Manufacturer Part Number: ADF4154BRUZ
• Description: IC FRAC-N FREQ SYNTH 16-TSSOP
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4154BRUZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 4GHz
• Divider/multiplier: No/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 4GHz
• Pll Type: Frequency Synthesis
• Frequency: 4GHz
• Supply Current: 20mA
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: TSSOP
• No. Of Pins: 16
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4154EBZ1 - BOARD EVALUATION FOR ADF4154EB1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. While the
device is operating, usually SW1 and SW2 are closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REF
RF INPUT STAGE
The RF input stage is shown in Figure 15. It is followed by a
two-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INPUT STAGE
RF
RF
IN
FROM RF
IN
IN
pin is not loaded while the device is powered down.
A
B
REF
IN
NC
POWER-DOWN
RF N-DIVIDER
SW1
GENERATOR
CONTROL
N COUNTER
Figure 14. Reference Input Stage
NO
BIAS
REG
INT
Figure 16. A and B Counters
NC
Figure 15. RF Input Stage
SW3
SW2
2kΩ
100kΩ
1.6V
2kΩ
BUFFER
MOD
REG
N = INT + FRAC/MOD
INTERPOLATOR
THIRD ORDER
FRACTIONAL
VALUE
FRAC
AGND
AV
TO R COUNTER
DD
TO PFD
Rev. A | Page 9 of 24
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced by
fractions of the PFD. See the RF Synthesizer: A Worked Example
section for more information. The RF VCO frequency (RF
equation is
where RF
controlled oscillator (VCO).
where:
REF
D is the REF
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD-1).
R-COUNTER
The 4-bit R-counter allows the input reference frequency
(REF
the PFD. Division ratios from 1 to 15 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
+IN
–IN
IN
IN
RF
F
is the reference input frequency.
PFD
) to be divided down to produce the reference clock to
HI
HI
OUT
OUT
=
=
REF
IN
is the output frequency of the external voltage-
D1
D2
F
doubler bit.
CLR1
CLR2
PFD
U1
U2
IN
Figure 17. PFD Simplified Schematic
Q1
Q2
×
×
(
(
1
UP
DOWN
INT
DELAY
+
D
+
)
(
R
FRAC
U3
MOD
)
)
CHARGE
PUMP
ADF4154
CP
OUT
(1)
(2)
)