CY23FP12OXC-002 Cypress Semiconductor Corp, CY23FP12OXC-002 Datasheet
CY23FP12OXC-002
Specifications of CY23FP12OXC-002
Related parts for CY23FP12OXC-002
CY23FP12OXC-002 Summary of contents
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... N Test Logic Function Selection S[2:1] VSSC Cypress Semiconductor Corporation Document #: 38-07644 Rev. ** Functional Description The CY23FP12-002 is a pre-programmed version of the CY23FP12. It features a high-performance fully field-program- mable 200 MHz zero delay buffer designed for high speed clock distribution. The integrated PLL is designed for low jitter and optimized for noise rejection ...
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Pin Description Pin Name I/O 1 REF2 I 2 REF1 I 3 CLKB0 O 4 CLKB1 PWR SSB 6 CLKB2 O 7 CLKB3 PWR DDB 9 V PWR SSB 10 CLKB4 O 11 ...
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REF /M FBK /N Below is a list of independent functions that can be programmed with a volume or prototype programmer on the “pre-programmed” silicon. Table 1. Configuration DC Drive Bank A Programs the drive strength of Bank A outputs. ...
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Table 1. (continued) Configuration Inv CLKB4 Generates an inverted clock on the CLKB4 output. When this option is programmed, CLKB4 and CLKB5 will become complimentary pairs. Pull-down Enable Enables/Disables internal pulldowns on all outputs Fbk Pull-down Enable Enables/Disables internal pulldowns ...
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Table list of output dividers that are independently selected to connect to each output pair. In the default (pre-programmed) state of the device, S1 and S2 pins will function, as indicated in Table 4. One possible example ...
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Absolute Maximum Conditions Parameter Description V Supply Voltage DD V Input Voltage REF IN V Input Voltage Except REF IN LU Latch-up Immunity I T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Operating Ambient A T Junction ...
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Switching Characteristics for CY23FP12-002SC/I Parameter Description [6] Reference Frequency Reference Edge Rate Reference Duty Cycle [7] t Output Frequency 1 [5] Duty Cycle [5] t Rise Time 3 [5] t Fall Time 4 [8,9] TTB Total Timing Budget, Bank A ...
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Switching Characteristics for CY23FP12-002SC/I Parameter Description t Tracking Skew tsk [5] t PLL Lock Time LOCK T Inserted Loop Delay LD Switching Waveforms Duty Cycle Timing 1.4V 1.4V All Outputs Rise/Fall Time 2.0V 2.0V OUTPUT 0.8V ...
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... Document #: 38-07644 Rev. ** © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...
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Document History Page Document Title: CY23FP12-002 200-MHz Field Programmable Zero Delay Buffer Document Number: 38-07644 Orig. of REV. ECN NO. Issue Date Change ** 206761 See ECN Document #: 38-07644 Rev. ** Description of Change RGL New Data Sheet CY23FP12-002 ...