CY23FP12OXC-002 Cypress Semiconductor Corp, CY23FP12OXC-002 Datasheet - Page 5

• Manufacturer Part Number: CY23FP12OXC-002
• Description: IC CLK ZDB 12OUT 200MHZ 28SSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr

Specifications of CY23FP12OXC-002

• Number Of Circuits: 1
• Package / Case: 28-SSOP
• Pll: Yes
• Input: LVCMOS, LVTTL
• Output: LVCMOS
• Ratio - Input:output: 2:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.5V, 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 200 MHz
• Minimum Input Frequency: 10 MHz
• Output Frequency Range: 10 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3692 - SOCKET ADAPTER FOR CY23FP12428-1918 - KIT DEV FTG PROGRAMMING KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Document #: 38-07644 Rev. **
Table 3 is a list of output dividers that are independently
selected to connect to each output pair.
In the default (pre-programmed) state of the device, S1 and S2
pins will function, as indicated in Table 4. One possible
example output is shown in this table. This example is for illus-
tration purposes only, since many other frequency combina-
tions are possible for each pre-programmed configuration.
Table 3.
Table 4. Pre-Programmed Configuration
Note:
ClkA0, A1
ClkA2, A3
ClkA4, A5
ClkB0, B1
ClkB2, B3
ClkB4, B5
ClkA0, A1
ClkA2, A3
ClkA4, A5
ClkB0, B1
ClkB2, B3
ClkB4, B5
ClkA0, A1
ClkA2, A3
ClkA4, A5
ClkB0, B1
ClkB2, B3
ClkB4, B5
ClkA0, A1
ClkA2, A3
ClkA4, A5
ClkB0, B1
ClkB2, B3
ClkB4, B5
1.
2.
Outputs S2, S1 DivSrc
Outputs will be rising edge aligned only to those outputs using this same device setting.
When the source of an output pair is set to [111], the output pair becomes lock indicator signal. For example, if the source of an output pair (CLKA0, CLKA1) is
set to [111], the CLKA0 and CLKA1, becomes lock indicator signals. In non-invert mode, CLKA0 and CLKA1 signals will be high when the PLL is in lock mode.
If CLKA0 is in an invert mode, the CLKA0 will be low and the CLKA1 will be high when the PLL is in lock mode.
CLKA/B Source
0 [000]
1 [001]
2 [010]
4 [100]
5 [101]
3 [011]
6 [110]
7 [111]
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
10
10
11
11
11
11
11
11
X=6
X=6
X=8
X=8
X=8
X=8
X=8
Ref
Ref
Ref
Ref
1
3
4
4
4
4
4
4
4
4
2
2
2
REF Input
TEST mode [LOCK signal]
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
100
100
100
100
100
100
100
100
100
100
100
100
25
25
25
25
25
25
Output Connects To
Example Output
Divide by 2X
Divide by X
Divide by 1
Divide by 2
Divide by 3
Divide by 4
VCO (MHz)
powerdown
powerdown
powerdown
powerdown
powerdown
powerdown
REF
266.6
266.6
266.6
266.6
266.6
266.6
200
200
200
200
200
200
200
200
200
200
200
200
[1]
Output
(MHz)
66.7
33.3
33.3
33.3
33.3
33.3
66.6
66.6
66.6
200
100
100
100
50
25
50
50
50
50
25
25
50
50
50
[2]
Field Programming the CY23FP12-002
The CY23FP12-002 is programmed at the package level, i.e.
in a programmer socket. The CY23FP12-002 is flash-
technology based, so the parts can be reprogrammed up to
100 times. This allows for fast and easy design changes and
product updates, and eliminates any issues with old and out-
of-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large production quantities.
CyberClocks Software
CyberClocks is an easy-to-use software application that
allows the user to custom-configure the CY23FP12-002.
Users can specify the REF, PLL frequency, output frequencies
and/or post-dividers, and different functional options. Cyber-
Clocks outputs an industry standard JEDEC file used for
programming the CY23FP12-002.
CyberClocks can be downloaded free of charge from the
Cypress website at www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY23FP12-002 and
program samples and small prototype quantities. The kit
comes with the latest version of CyberClocks and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyberClocks can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
CY23FP12-002 Frequency Calculation
The CY23FP12-002 is an extremely flexible clock buffer with
up to twelve individual outputs, generated from an integrated
PLL.
There are four variables used to determine the final output
frequency. These are the input Reference Frequency M, the N
dividers, and the post divider X.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs pair has many output options available to it.
There are six post divider options: /1, /2, /3, /4, /X, and /2X.
The post divider options can be applied to the calculated PLL
frequency or to the REF directly. The feedback either is
connected to CLKA0 internally or connected to any output
externally.
A programmable divider, M, is inserted between the reference
input, REF, and the phase detector. The divider M can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
A programmable divider, N, is inserted between the feedback
input, FBK, and the phase detector. The divider N can be any
integer 1 to 256. The PLL input frequency cannot be lower than
10 MHz or higher than 200 MHz.
So the output can be calculated as following:
F
F
F
In addition to above divider options, the another option
bypasses the PLL and passes the REF directly to the output.
F
REF
PLL
OUT
OUT
= (F
/ M = F
= F
= F
PLL
REF
REF
.
/ post divider.
FBK
* N *
/ N.
post divider)/M.
CY23FP12-002
Page 5 of 10
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