CY23FP12OXC-002 Cypress Semiconductor Corp, CY23FP12OXC-002 Datasheet - Page 7

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CY23FP12OXC-002

Manufacturer Part Number
CY23FP12OXC-002
Description
IC CLK ZDB 12OUT 200MHZ 28SSOP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Zero Delay Bufferr
Datasheet

Specifications of CY23FP12OXC-002

Number Of Circuits
1
Package / Case
28-SSOP
Pll
Yes
Input
LVCMOS, LVTTL
Output
LVCMOS
Ratio - Input:output
2:12
Differential - Input:output
No/No
Frequency - Max
200MHz
Divider/multiplier
Yes/No
Voltage - Supply
2.5V, 3.3V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Frequency-max
200MHz
Maximum Input Frequency
200 MHz
Minimum Input Frequency
10 MHz
Output Frequency Range
10 MHz to 200 MHz
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY3692 - SOCKET ADAPTER FOR CY23FP12428-1918 - KIT DEV FTG PROGRAMMING KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Document #: 38-07644 Rev. **
Switching Characteristics for CY23FP12-002SC/I
t
t
t
TTB
t
t
t
t
Notes:
1
3
4
5
6
7
J
Parameter
5.
6.
7.
8.
9.
All parameters are specified with loaded outputs.
When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the reference frequency can be lower than 10MHz. With auto power-
down disabled and PLL power-down enabled, the reference frequency can be as low as DC level.
When the device is configured as a non-PLL fanout buffer (PLL Power-down enabled), the output frequency can be lower than 10MHz. With auto power-down
disabled and PLL power-down enabled, the output frequency can be as low as DC level.
Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply
voltage, operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output
skew, cycle-cycle jitter, and dynamic phase error.TTB will be equal to or smaller than the maximum specified value at a given frequency.
Reference Frequency
Reference Edge Rate
Reference Duty Cycle
Output Frequency
Duty Cycle
Rise Time
Fall Time
Total Timing Budget,
Bank A and B same
frequency
Total Timing Budget, Bank
A and B different frequency
Output to Output Skew
Bank to Bank Skew
Bank to Bank Skew
Bank to Bank Skew
Input to Output Skew (static
phase offset)
Device to Device Skew
Cycle to Cycle Jitter
(Peak-to-peak)
Cycle to Cycle Jitter
(Peak-to-peak)
Description
[5]
[5]
[5]
[5]
[7]
[5]
[5]
[8,9]
[6]
[5]
[5]
C
C
C
C
V
V
V
C
V
C
V
C
V
C
V
C
V
C
V
C
V
C
Outputs @200 MHz, tracking skew not
included
All outputs equally loaded
Same frequency
Different frequency
Different voltage, same frequency
Measured at V
Measured at V
Bank A and B same frequency
Bank A and B different frequency
L
L
L
L
DDA/B
DDA/B
DDA/B
L
DDA/B
L
DDA/B
L
DDA/B
L
DDA/B
L
DDA/B
L
DDA/B
L
DDA/B
L
= 15 pF, Commercial Temperature
= 15 pF, Industrial Temperature
= 30 pF, Commercial Temperature
= 30 pF, Industrial Temperature
= 30 pF (standard drive and high drive)
= 15 pF (standard drive and high drive)
= 30 pF (high drive only)
= 15 pF (high drive only)
= 30 pF (standard drive and high drive)
= 15 pF (standard drive and high drive)
= 30 pF (high drive only)
= 15 pF (high drive only)
= 3.3V, measured at V
= 2.5V
= 3.3V, 0.8V to 2.0V,
= 3.3V, 0.8V to 2.0V,
= 2.5V, 0.6V to 1.8V,
= 2.5V, 0.6V to 1.8V,
= 3.3V, 0.8V to 2.0V,
= 3.3V, 0.8V to 2.0V,
= 2.5V, 0.6V to 1.8V,
= 2.5V, 0.6V to 1.8V,
Test Conditions
DD
DD
/2, REF to FBK
/2
[5]
DD
/2
Min.
45.0
40.0
10
25
10
10
10
10
1
Typ.
50.0
50.0
CY23FP12-002
0
0
166.7
Max.
83.3
55.0
60.0
200
200
100
650
850
200
200
400
400
250
500
200
400
1.6
0.8
2.0
1.0
1.6
0.8
1.6
0.8
75
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MHz
V/ns
MHz
Unit
ns
ns
ps
ps
ps
ps
ps
%
%
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