AD9516-0BCPZ Analog Devices Inc, AD9516-0BCPZ Datasheet - Page 39

• Manufacturer Part Number: AD9516-0BCPZ
• Description: IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-0BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.95GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 2.8GHz
• No. Of Outputs: 14
• No. Of Multipliers / Dividers: 32
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

VCO Calibration
The AD9516 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be present.
During the first initialization after a power-up or a reset of the
AD9516, a VCO calibration sequence is initiated by setting
Register 0x018[0] = 1b. This can be done as part of the initial
setup, before executing update registers (Register 0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting Register 0x018[0] = 0b, executing an update
registers operation, setting Register 0x018[0] = 1b, and executing
another update registers operation. A readback bit, Bit 6 in
Register 0x01F, indicates when a VCO calibration is finished
by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
•
•
•
•
•
•
•
•
Program the PLL registers to the proper values for the PLL
loop. Note that that automatic holdover mode must be
disabled, and the VCO divider must not be set to “Static. ”
Ensure that the input reference signal is present.
For the initial setting of the registers after a power-up or reset,
initiate VCO calibration by setting Register 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set
Register 0x018[0] = 0b, update registers; and then set
Register 0x018[0] = 1b, update registers.
A SYNC operation is initiated internally, causing the
outputs to go to a static state determined by normal SYNC
function operation.
VCO calibrates to the desired setting for the requested
VCO frequency.
Internally, the SYNC signal is released, allowing outputs to
continue clocking.
PLL loop is closed.
PLL locks.
REFIN (REF1)
REFIN (REF2)
BYPASS
CLK
CLK
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
N DIVIDER
Figure 54. Reference and VCO Status Monitors
DIVIDER
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. A | Page 39 of 80
0
1
VCO STATUS
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
A sync is executed during the VCO calibration; therefore, the
outputs of the AD9516 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 54
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
where:
f
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Table 29. Example Time to Complete a VCO Calibration
with Different f
f
100
10
10
REFIN
REFIN
f
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
(MHz)
is the frequency of the REFIN signal.
CAL_CLOCK
= f
FREQUENCY
R Divider
1
10
100
DETECTOR
REFIN
DETECT
REFIN
PHASE
LOCK
/(R × cal_div)
Frequencies
CPRSET VCP
PFD
100 MHz
1 MHz
100 kHz
CHARGE
PUMP
HOLD
Time to Calibrate VCO
88 μs
8.8 ms
88 ms
AD9516-0
LD
CP
STATUS