AD9516-0BCPZ Analog Devices Inc, AD9516-0BCPZ Datasheet - Page 76

• Manufacturer Part Number: AD9516-0BCPZ
• Description: IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9516-0BCPZ

• Pll: Yes
• Input: Clock
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:14
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.95GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 2.8GHz
• No. Of Outputs: 14
• No. Of Multipliers / Dividers: 32
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9516-0
Table 60. VCO Divider and CLK Input
Reg.
Addr
(Hex)
0x1E0
0x1E1
0x1E1
Table 61. System
Reg.
Addr.
(Hex)
0x230
Table 62. Update All Registers
Reg.
Addr
(Hex)
0x232
Bits
[2:0]
4
3
2
1
0
Bits
2
1
0
Bits
0
Name
Power down SYNC
Power down distribution reference
Soft SYNC
Name
Update all registers
Name
VCO divider
Power down clock input section
Power down VCO clock interface
Power down VCO and CLK
Select VCO or CLK
Bypass VCO divider
Description
2
0
0
0
0
1
1
1
1
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Description
Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is,
it does not have to be set back to 0.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
1
0
0
1
1
0
0
1
1
Rev. A | Page 76 of 80
0
0
1
0
1
0
1
0
1
Divide
2.
3.
4 (default).
5.
6.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.