MPC9658AC IDT, Integrated Device Technology Inc, MPC9658AC Datasheet

MPC9658AC

Manufacturer Part Number

MPC9658AC

Description

IC PLL CLK GEN 1:10 3.3V 32-LQFP

Manufacturer

IDT, Integrated Device Technology Inc

Type

PLL Clock Generatorr

Datasheet

1.MPC9658ACR2.pdf (11 pages)

Specifications of MPC9658AC

Pll

Yes with Bypass

Input

LVPECL

Output

LVCMOS

Number Of Circuits

Ratio - Input:output

1:10

Differential - Input:output

Yes/No

Frequency - Max

250MHz

Divider/multiplier

Yes/No

Voltage - Supply

3.135 V ~ 3.465 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

32-LQFP

Frequency-max

250MHz

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

MPC9658AC

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

Company:

BOSTOCK HK LIMITED

Part Number:

MPC9658ACR2

Manufacturer:

IDT, Integrated Device Technology Inc

Quantity:

10 000

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3.3V 1:10 LVCMOS PLL

CLOCK GENERATOR

IDT™ / ICS™ 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR

3.3 V 1:10 LVCMOS PLL Clock

Generator

zero-delay buffer targeted for high performance low-skew clock distribution in

mid-range to high-performance telecom, networking and computing applications.

With output frequencies up to 250 MHz and output skews less than 120 ps the

device meets the needs of the most demanding clock applications. The

MPC9658 is specified for the temperature range of 0°C to +70°C.

Features

•

Functional Description

input reference clock. Normal operation of the MPC9658 requires the connection

of the QFB output to the feedback input to close the PLL feedback path (external

feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects

the operating frequency range of 50 to 125 MHz or 100 to 250 MHz. The two available post-PLL dividers selected by VCO_SEL

(divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the

VCO frequency range. The internal VCO of the MPC9658 is running at either 2x or 4x of the reference clock frequency.

as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

lected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL by-

pass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply.

The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes

the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close

the phase locked loop, enabling the PLL to recover to normal operation.

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω trans-

mission lines. For series terminated transmission lines, each of the MPC9658 outputs can drive one or two traces giving the de-

vices an effective fanout of 1:16. The device is packaged in a 7x7 mm

The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and

The MPC9658 utilizes PLL technology to frequency lock its outputs onto an

The MPC9658 has a differential LVPECL reference input along with an external feedback input. The MPC9658 is ideal for use

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the se-

The MPC9658 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

1:10 PLL based low-voltage clock generator

Supports zero-delay operation

3.3 V power supply

Generates clock signals up to 250 MHz

Maximum output skew of 120 ps

Differential LVPECL reference clock input

External PLL feedback

Drives up to 20 clock lines

32-lead LQFP packaging

32-lead Pb-free Package Available

Pin and function compatible to the MPC958

32-lead LQFP package.

PLL CLOCK GENERATOR

32-LEAD LQFP PACKAGE

3.3 V LVCMOS 1:10

MPC9658 REV 6 SEPTEMBER 29, 2006

Pb-FREE PACKAGE

MPC9658

LOW VOLTAGE

CASE 873A-03

FA SUFFIX

AC SUFFIX

MPC9658

Related parts for MPC9658AC

MPC9658AC Summary of contents

Page 1

LVCMOS PLL CLOCK GENERATOR 3.3 V 1:10 LVCMOS PLL Clock Generator The MPC9658 is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, ...

Page 2

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR V CC PCLK 25 k PCLK 25 k FB_IN 3⋅25 k PLL_EN VCO_SEL BYPASS MR/ VCO_SEL IDT™ / ICS™ 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR ÷ ...

Page 3

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 1. Pin Configurations Number Name PCLK, PCLK Input FB_IN Input VCO_SEL Input BYPASS Input PLL_EN Input MR/OE Input Q0–9 Output QFB Output GND Supply V Supply CC_PLL V Supply CC Table 2. ...

Page 4

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 4. General Specifications Symbol Characteristics V Output Termination Voltage TT MM ESD Protection (Machine Model) HBM ESD Protection (Human Body Model) LU Latch-Up Immunity C Power Dissipation Capacitance PD C Input Capacitance ...

Page 5

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Table 6. AC Characteristics (V CC Symbol f Input reference frequency REF PLL mode, external feedback Input reference frequency in PLL bypass mode f VCO lock frequency range VCO f Output Frequency MAX ...

Page 6

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Programming the MPC9658 The MPC9658 supports output clock frequencies from 50 to 250 MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) ...

Page 7

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Calculation of Part-to-Part Skew The MPC9658 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more MPC9658 are ...

Page 8

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR MPC958 Output Buffer = 36 Ω Ω In MPC958 Output = 36 Ω R Buffe S 14 Ω Ω Figure 6. Single versus Dual Transmission ...

Page 9

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR t SK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output-to-Output Skew ...

Page 10

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR D1 D1/2 PIN 1 INDEX E1 D/2 4X 0. 28X SEATING PLANE C DETAIL AD 8X (θ1˚ (S) ...

Page 11

MPC9658 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States ...

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