MPC9658AC IDT, Integrated Device Technology Inc, MPC9658AC Datasheet - Page 6

• Manufacturer Part Number: MPC9658AC
• Description: IC PLL CLK GEN 1:10 3.3V 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of MPC9658AC

• Pll: Yes with Bypass
• Input: LVPECL
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ / ICS™ 3.3V 1:10 LVCMOS PLL CLOCK GENERATOR
MPC9658
3.3V 1:10 LVCMOS PLL CLOCK GENERATOR
Programming the MPC9658
to 250 MHz. Two different feedback divider configurations
can be used to achieve the desired frequency operation
range. The feedback divider (VCO_SEL) should be used to
situate the VCO in the frequency lock range between 200 and
500 MHz for stable and optimal operation. Two operating
Table 7. MPC9658 Configurations (QFB connected to FB_IN)
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the V
characteristics, for instance I/O jitter. The MPC9658 provides
separate power supplies for the output buffers (V
phase-locked loop (V
this design technique is to isolate the high switching noise
digital outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simple but
effective form of isolation is a power supply filter on the
V
power supply filter scheme. The MPC9658 frequency and
phase stability is most susceptible to noise with spectral
content in the 100 kHz to 20 MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop across the series filter resistor R
the I
V
that a minimum of 2.835 V must be maintained on the
V
BYPASS
CC_PLL
CC_PLL
CC_PLL
The MPC9658 supports output clock frequencies from 50
The MPC9658 is a mixed analog/digital product. Its analog
CC_PLL
0
1
1
1
1
V
CC
CCA_PLL
pin) is typically 12 mA (20 mA maximum), assuming
pin for the MPC9658.
pin.
Figure 3. V
current (the current sourced through the
PLL_EN
X
0
0
1
1
power supply impacts the device
R
F
R
= 5–15 Ω
CCA_PLL
F
CC_PLL
VCO_SEL
C
F
X
0
1
0
1
33...100 nF
) of the device. The purpose of
Power Supply Filter
Figure 3
C
F
10 nF
= 22 μF
Test mode: PLL and divider bypass
PLL mode (high frequency range)
PLL mode (low frequency range)
F
. From the data sheet
illustrates a typical
Test mode: PLL bypass
Test mode: PLL bypass
V
V
APPLICATIONS INFORMATION
CC_PLL
CC
Operation
CC
MPC9658
) and the
6
frequency ranges are supported: 50 to 125 MHz and 100 to
250 MHz.
to FB_IN)
MPC9658. PLL zero-delay is supported if BYPASS = 1,
PLL_EN = 1, and the input frequency is within the specified
PLL reference frequency range.
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in
3
42 dB.
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC9658 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC9658 in Zero-Delay Applications
MPC9658. Designs using the MPC9658 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9658 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
–
The minimum values for R
As the noise frequency crosses the series resonant point
Nested clock trees are typical applications for the
f
f
5 kHz and the noise attenuation at 100 kHz is better than
Q0–9
Q0–9
f
f
f
Q0–9
Q0–9
Q0–9
Ratio
= f
= f
Table 7. MPC9658 Configurations (QFB connected
= f
= f
= f
illustrates the configurations supported by the
REF
REF
REF
REF
REF
÷ 2
÷ 4
Figure
Output range (f
3, the filter cut-off frequency is around
100 – 250 MHz
50 – 125 MHz
0 – 62.5 MHz
0 – 250 MHz
0 – 125 MHz
Frequency
MPC9658 REV 6 SEPTEMBER 29, 2006
F
and the filter capacitor C
Q0–9
)
f
f
VCO
VCO
VCO
= f
= f
n/a
n/a
n/a
REF
REF
F
⋅ 2
⋅ 4
are