MPC9608AC IDT, Integrated Device Technology Inc, MPC9608AC Datasheet - Page 6

• Manufacturer Part Number: MPC9608AC
• Description: IC CLOCK BUFFER ZD 1:10 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC9608AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 1:10 LVCMOS Zero Delay Clock Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9608
1:10 LVCMOS Zero Delay Clock Buffer
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the V
characteristics, for instance I/O jitter. The MPC9608 provides
separate power supplies for the output buffers (V
phase-locked loop (V
design technique is to isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase-locked loop. In a digital system environment where it is
more difficult to minimize noise on the power supplies a second
level of isolation may be required. The simple but effective form
of isolation is a power supply filter on the V
MPC9608.
scheme. The MPC9608 frequency and phase stability is most
susceptible to noise with spectral content in the 100 kHz to 20
MHz range. Therefore the filter should be designed to target this
range. The key parameter that needs to be met in the final filter
design is the DC voltage drop across the series filter resistor R
From the data sheet the I
through the V
assuming that a minimum of 3.125 V must be maintained on the
V
resistance of 9
criteria.
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in
and the noise attenuation at 100 kHz is better than 42 dB.
an individual capacitor, its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9608 has several
design features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL),
there still may be applications in which overall performance is
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
V
CCA
The MPC9608 is a mixed analog/digital product. Its analog
CC
The minimum values for R
As the noise frequency crosses the series resonant point of
R
CCA
pin. The resistor R
F
= 9-10 Ω for V
Figure
(PLL) power supply impacts the device
Figure 3
Figure 3. V
CCA
–
3, the filter cut-off frequency is around 3-5 kHz
10 Ω (V
pin) is typically 4 mA (8 mA maximum),
CC
illustrates a typical power supply filter
R
CCA
F
= 3.3 V
33...100 nF
C
CCA
F
CC
F
) of the device. The purpose of this
CCA
shown in
= 3.3 V) to meet the voltage drop
Power Supply Filter
F
current (the current sourced
and the filter capacitor C
10 nF
C
Figure 3
F
= 1 µF for V
CCA
must have a
V
MPC9608
V
CCA
pin for the
CC
CC
CC
APPLICATIONS INFORMATION
= 3.3 V
) and the
F
are
F
.
6
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems in
most designs.
Using the MPC9608 in Zero-delay Applications
Designs using the MPC9608, as LVCMOS PLL fanout buffer
with zero insertion delay, will show significantly lower clock
skew than clock distributions developed from CMOS fanout
buffers. The external feedback option of the MPC9608 clock
driver allows for its use as a zero delay buffer. By using the QFB
output as a feedback to the PLL the propagation delay through
the device is virtually eliminated. The PLL aligns the feedback
clock output edge with the clock input reference edge resulting
in a near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This effective
delay consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
Calculation of Part-to-Part Skew
critical clock signal timing can be maintained across several
devices. If the reference clock inputs of two or more MPC9608
are connected together, the maximum overall timing uncertainty
from the common CCLK input to any output is:
nents: static phase offset, output skew, feedback board trace
delay, and I/O (phase) jitter:
CCLK
Any Q
Any Q
Nested clock trees are typical applications for the MPC9608.
The MPC9608 zero delay buffer supports applications where
QFB
Figure 4. MPC9608 maximum device-to-device skew
Max. skew
QFB
t
This maximum timing uncertainty consists of 4 compo-
SK(PP)
Common
Device 1
Device 1
Device 2
Device2
= t
(
∅
)
+ t
t
SK(O)
JIT(∅)
-t
(∅)
+t
+ t
SK(O)
PD, LINE(FB)
+t
(∅)
t
JIT(∅)
t
SK(PP)
+ t
JIT(
t
+t
PD,LINE(FB)
∅
SK(O)
)
.
MPC9608
CF
NETCOM
MPC9608
479