MPC9608AC IDT, Integrated Device Technology Inc, MPC9608AC Datasheet - Page 7

• Manufacturer Part Number: MPC9608AC
• Description: IC CLOCK BUFFER ZD 1:10 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC9608AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 1:10 LVCMOS Zero Delay Clock Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9608
1:10 LVCMOS Zero Delay Clock Buffer
MPC9608
is specified. I/O jitter numbers for other confidence factors (CF)
can be derived from
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter
confidence factor of 99.7% (± 3σ) is assumed, resulting in a
worst case timing uncertainty from input to any output of -295
ps to 295 ps
Driving Transmission Lines
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20 Ω the drivers can drive ei-
ther parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to Mo-
torola application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50 Ω
resistance to V
thus only a single terminated line can be driven by each output
of the MPC9608 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines.
driving a single series terminated line versus two series
terminated lines in parallel. When taken to its extreme, the
fanout of the MPC9608 clock driver is effectively doubled due to
its capability to drive multiple lines.
1. Skew data are designed targets and pending device specifications.
480
Table 8. Confidence Factor CF
Due to the statistical nature of I/O jitter, an RMS value (1 σ)
The feedback trace delay is determined by the board layout
This technique draws a fairly high level of DC current and
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
CF
t
t
The MPC9608 clock driver was designed to drive high
SK(PP)
SK(PP)
=
=
(1)
Probability of clock edge within the distribution
CC
relative to CCLK:
÷ 2.
[-100 ps...100 ps] + [-150 ps...150 ps] +
[(15 ps
[-295 ps...295 ps] + t
Table 8.
.
-3)...(15 ps
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
Figure 5
.
PD, LINE(FB)
3)] + t
illustrates an output
PD, LINE(FB)
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
7
Waveforms
single line versus two lines. In both cases the drive capability of
the MPC9608 output buffer is more than sufficient to drive 50 Ω
transmission lines on the incident edge. From the delay
measurements in the simulations a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that
the dual line driving need not be used exclusively to maintain
the tight output-to-output skew of the MPC9608. The output
waveform in
step in the waveform. This step is caused by the impedance
mismatch seen looking into the driver. The parallel combination
of the 36 Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
near unity reflection coefficient. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
At the load end the voltage will double to 2.6 V due to the
IN
IN
The waveform plots in
Figure 5. Single versus Dual Transmission Lines
MPC9608
MPC9608
OUTPUT
OUTPUT
BUFFER
BUFFER
14 Ω
14 Ω
show the simulation results of an output driving a
Figure 6. Single versus Dual Waveforms
V
Z
R
R
V
0
L
S
0
L
= V
= 50 Ω || 50 Ω
= 36 Ω || 36 Ω
= 14 Ω
= 3.0 (25 ÷ (18 + 17 + 25))
= 1.31 V
S
(Z
R
R
R
Figure 6. Single versus Dual
S
S
S
0
= 36 Ω
= 36 Ω
= 36 Ω
÷ (R
S
+ R
Z
Z
Z
O
O
O
0
= 50 Ω
= 50 Ω
= 50 Ω
+ Z
0
))
OutA
OutB0
OutB1
shows a
NETCOM
MPC9608