MPC9608AC IDT, Integrated Device Technology Inc, MPC9608AC Datasheet - Page 9

• Manufacturer Part Number: MPC9608AC
• Description: IC CLOCK BUFFER ZD 1:10 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC9608AC

• Pll: Yes with Bypass
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:10
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IDT™ 1:10 LVCMOS Zero Delay Clock Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9608
1:10 LVCMOS Zero Delay Clock Buffer
MPC9608
482
The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL
controlled edges, expressed as a percentage.
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent
cycle pairs.
The pin-to-pin skew is defined as the worst case difference in propagation delay between any
similar delay path within a single device.
t
Figure 15. Output Transition Time Test Reference
F
Figure 9. Output-to-Output Skew t
Figure 11. Output Duty Cycle (DC)
Figure 13. Cycle-to-Cycle Jitter
T
N
t
P
T
N + 1
T
0
DC = t
t
R
t
SK(O)
T
P
JIT(CC)
/T
V
CC
0
0.55
x 100%
2.4
= 3.3 V
= |T
N
-T
SK(O)
V
V
GND
CC
CC
N + 1
V
V
GND
V
V
GND
CC
CC
CC
CC
÷
÷
÷
2
|
2
2
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
9
The deviation in t
The deviation in cycle time of a signal with respect to the ideal period over a random sample of cy-
cles.
CLK_STOP
CCLK
Figure 10. Propagation Delay (t
Figure 16. Setup and Hold Time (t
FB_IN
CCLK
FB_IN
CCLK
0
for a controlled edge with respect to a t
T
0
Figure 14. Period Jitter
t
Figure 12. I/O Jitter
(∅)
Test Reference
t
s
t
H
T
T
PD
JIT(∅)
JIT(PER)
0
mean in a random sample of cycles.
, static phase offset)
s
, t
= |T
H
) Test Reference
= |T
0
- T
N
1
- 1/f
mean|
V
V
GND
V
V
GND
V
V
GND
V
V
GND
0
CC
CC
CC
CC
CC
CC
CC
CC
|
÷
÷
÷
÷
NETCOM
2
2
2
2
MPC9608