MPC961CAC IDT, Integrated Device Technology Inc, MPC961CAC Datasheet - Page 5

• Manufacturer Part Number: MPC961CAC
• Description: IC BUFFER ZD 1:18 PLL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Zero Delay Bufferr

Specifications of MPC961CAC

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:17
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: No/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MPC961C Data Sheet
Power Supply Filtering
exhibits some sensitivities that would not necessarily be seen on a
fully digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power supply
pins. The MPC961C provides separate power supplies for the
output buffers (V
device. The purpose of this design technique is to isolate the high
switching noise digital outputs from the relatively sensitive internal
analog phase-locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However, in a
digital system environment where it is more difficult to minimize
noise on the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply filter on the
V
MPC961C is most susceptible to noise with spectral content in the
10 kHz to 10 MHz range. Therefore the filter should be designed to
target this range. The key parameter that needs to be met in the final
filter design is the DC voltage drop that will be seen between the V
supply and the V
I
2 mA (5 mA maximum), assuming that a minimum of 2.375 V
(V
The resistor R
(V
criteria. The RC filter pictured will provide a broadband filter with
approximately 100:1 attenuation for noise whose spectral content is
above 20 kHz. As the noise frequency crosses the series resonant
point of an individual capacitor it's overall impedance begins to look
inductive and thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance path to
ground exists for frequencies well above the bandwidth of the PLL.
the susceptibility to power supply noise (isolated power and grounds
and fully differential PLL) there still may be applications in which
overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
MPC961C REVISION 5 AUGUST 17, 2009
CCA
CCA
CC
CC
The MPC961C is a mixed analog/digital product and as such it
Figure 3
Although the MPC961C has several design features to minimize
current (the current sourced through the V
= 3.3 V or V
= 3.3 V) or 5 to 15 Ω (V
V
pin for the MPC961C.
CC
illustrates a typical power supply filter scheme. The
F
shown in
CC
CCA
CC
Figure 3. Power Supply Filter
R
R
) and the phase-locked loop (V
F
F
R
= 270 Ω for V
= 5–15 Ω for V
= 2.5 V) must be maintained on the V
F
pin of the MPC961C. From the data sheet the
C
Figure 3
F
33...100 nF
CC
CC
CC
= 2.5 V) to meet the voltage drop
10 nF
= 3.3 V
= 2.5 V
must have a resistance of 270 Ω
V
V
CCA
CC
CCA
MPC961C
CCA
pin) is typically
APPLICATIONS INFORMATION
) of the
CCA
pin.
CC
5
Driving Transmission Lines
signals in a terminated transmission line environment. To provide
the optimum flexibility to the user the output drivers were designed
to exhibit the lowest impedance possible. With an output impedance
of less than 15 Ω the drivers can drive either parallel or series
terminated transmission lines. For more information on transmission
lines the reader is referred to the Application Note AN1091.
distribution of signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated transmission
lines can be used. The parallel technique terminates the signal at
the end of the line with a 50 Ω resistance to V
draws a fairly high level of DC current and thus only a single
terminated line can be driven by each output of the MPC961C clock
driver. For the series terminated case however there is no DC
current draw, thus the outputs can drive multiple series terminated
lines.
line vs two series terminated lines in parallel. When taken to its
extreme the fanout of the MPC961C clock driver is effectively
doubled due to its capability to drive multiple lines.
output driving a single line verses two lines. In both cases the drive
capability of the MPC961C output buffer is more than sufficient to
drive 50 Ω transmission lines on the incident edge. Note from the
delay measurements in the simulations a delta of only 43 ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC961C. The output waveform in
Figure 5
impedance mismatch seen looking into the driver. The parallel
combination of the 36 Ω series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
IN
IN
The MPC961C clock driver was designed to drive high speed
In most high performance clock networks point-to-point
The waveform plots of
Figure 4
Figure 4. Single versus Dual Transmission Lines
shows a step in the waveform, this step is caused by the
MPC961
MPC961
Output
Output
Buffer
Buffer
14 Ω
14 Ω
illustrates an output driving a single series terminated
R
R
R
S
S
S
Figure 5
= 36 Ω
= 36 Ω
= 36 Ω
©2009 Integrated Device Technology, Inc.
LOW VOLTAGE ZERO DELAY BUFFER
show the simulation results of an
Z
Z
Z
O
O
O
= 50 Ω
= 50 Ω
= 50 Ω
CC
/2. This technique
OutA
OutB0
OutB1